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| author | Jim Quinlan <james.quinlan@broadcom.com> | 2026-01-05 12:34:19 -0500 |
|---|---|---|
| committer | Greg Kroah-Hartman <gregkh@linuxfoundation.org> | 2026-01-08 10:15:04 +0100 |
| commit | b4e2b74f69781ba034266aca355822bfd298a2cf (patch) | |
| tree | b93c44a6e9f5104ad14eb5ea417e041e827a9717 /include/net/aligned_data.h | |
| parent | 8d185636a6299ff9d2e9eec3a4a25026c13d2351 (diff) | |
PCI: brcmstb: Set MLW based on "num-lanes" DT property if present
[ Upstream commit a364d10ffe361fb34c3838d33604da493045de1e ]
By default, the driver relies on the default hardware defined value for the
Max Link Width (MLW) capability. But if the "num-lanes" DT property is
present, assume that the chip's default capability information is incorrect
or undesired, and use the specified value instead.
Signed-off-by: Jim Quinlan <james.quinlan@broadcom.com>
[mani: reworded the description and comments]
Signed-off-by: Manivannan Sadhasivam <mani@kernel.org>
Reviewed-by: Florian Fainelli <florian.fainelli@broadcom.com>
Link: https://patch.msgid.link/20250530224035.41886-3-james.quinlan@broadcom.com
Stable-dep-of: 9583f9d22991 ("PCI: brcmstb: Fix disabling L0s capability")
Signed-off-by: Sasha Levin <sashal@kernel.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Diffstat (limited to 'include/net/aligned_data.h')
0 files changed, 0 insertions, 0 deletions