diff options
| author | Vladimir Zapolskiy <vz@mleia.com> | 2025-09-04 21:46:42 +0300 |
|---|---|---|
| committer | Sasha Levin <sashal@kernel.org> | 2026-03-04 07:19:37 -0500 |
| commit | 8461f646f68a02a97f81fe202f50c62cda122520 (patch) | |
| tree | 72c1958f0c3357dead36cdbd1f2912aca2411665 /arch | |
| parent | 87a1f93986aa1500b85aeff16b0b71c29ea116ea (diff) | |
ARM: dts: lpc32xx: Set motor PWM #pwm-cells property value to 3 cells
[ Upstream commit 65ae9ea77e1f2a20ad2866f99596df7ccdbd3b95 ]
Since commit 4cd2f417a0ac ("dt-bindings: pwm: Convert lpc32xx-pwm.txt
to yaml format") both types of PWM controlles on NXP LPC32xx SoC
fairly gained 3 cells, reflect it in the platform dtsi file.
The change removes a dt binding checker warning:
mpwm@400e8000: #pwm-cells:0:0: 3 was expected
Cc: Uwe Kleine-König <u.kleine-koenig@baylibre.com>
Acked-by: Uwe Kleine-König <u.kleine-koenig@baylibre.com>
Reviewed-by: Frank Li <Frank.Li@nxp.com>
Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
Stable-dep-of: 71630e581a0e ("arm: dts: lpc32xx: add clocks property to Motor Control PWM device tree node")
Signed-off-by: Sasha Levin <sashal@kernel.org>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm/boot/dts/nxp/lpc/lpc32xx.dtsi | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm/boot/dts/nxp/lpc/lpc32xx.dtsi b/arch/arm/boot/dts/nxp/lpc/lpc32xx.dtsi index 974410918f35..770e85b8268f 100644 --- a/arch/arm/boot/dts/nxp/lpc/lpc32xx.dtsi +++ b/arch/arm/boot/dts/nxp/lpc/lpc32xx.dtsi @@ -301,8 +301,8 @@ mpwm: mpwm@400e8000 { compatible = "nxp,lpc3220-motor-pwm"; reg = <0x400e8000 0x78>; + #pwm-cells = <3>; status = "disabled"; - #pwm-cells = <2>; }; }; |