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<title>kernel/tools/testing/selftests/rseq/rseq-riscv.h, branch linux-rolling-stable</title>
<subtitle>Hosts the 0x221E linux distro kernel.</subtitle>
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<updated>2025-09-16T05:23:52Z</updated>
<entry>
<title>KVM: riscv: selftests: Use the existing RISCV_FENCE macro in `rseq-riscv.h`</title>
<updated>2025-09-16T05:23:52Z</updated>
<author>
<name>Quan Zhou</name>
<email>zhouquan@iscas.ac.cn</email>
</author>
<published>2025-09-01T07:35:49Z</published>
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<id>urn:sha1:c92786e179e0def2cf9a8003e7be0fcba73afb15</id>
<content type='text'>
To avoid redefinition issues with RISCV_FENCE, directly reference
the existing macro in `rseq-riscv.h`.

Signed-off-by: Quan Zhou &lt;zhouquan@iscas.ac.cn&gt;
Signed-off-by: Dong Yang &lt;dayss1224@gmail.com&gt;
Reviewed-by: Andrew Jones &lt;ajones@ventanamicro.com&gt;
Link: https://lore.kernel.org/r/85e5e51757c9289ca463fbc4ba6d22f9c9db791b.1756710918.git.dayss1224@gmail.com
Signed-off-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
<entry>
<title>rseq/selftests: Fix riscv rseq_offset_deref_addv inline asm</title>
<updated>2025-02-14T21:06:36Z</updated>
<author>
<name>Stafford Horne</name>
<email>shorne@gmail.com</email>
</author>
<published>2025-01-14T17:07:21Z</published>
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<id>urn:sha1:713e788c0e07e185fd44dd581f74855ef149722f</id>
<content type='text'>
When working on OpenRISC support for restartable sequences I noticed
and fixed these two issues with the riscv support bits.

 1 The 'inc' argument to RSEQ_ASM_OP_R_DEREF_ADDV was being implicitly
   passed to the macro.  Fix this by adding 'inc' to the list of macro
   arguments.
 2 The inline asm input constraints for 'inc' and 'off' use "er",  The
   riscv gcc port does not have an "e" constraint, this looks to be
   copied from the x86 port.  Fix this by just using an "r" constraint.

I have compile tested this only for riscv.  However, the same fixes I
use in the OpenRISC rseq selftests and everything passes with no issues.

Fixes: 171586a6ab66 ("selftests/rseq: riscv: Template memory ordering and percpu access mode")
Signed-off-by: Stafford Horne &lt;shorne@gmail.com&gt;
Tested-by: Charlie Jenkins &lt;charlie@rivosinc.com&gt;
Reviewed-by: Charlie Jenkins &lt;charlie@rivosinc.com&gt;
Reviewed-by: Mathieu Desnoyers &lt;mathieu.desnoyers@efficios.com&gt;
Acked-by: Shuah Khan &lt;skhan@linuxfoundation.org&gt;
Cc: stable@vger.kernel.org
Link: https://lore.kernel.org/r/20250114170721.3613280-1-shorne@gmail.com
Signed-off-by: Palmer Dabbelt &lt;palmer@rivosinc.com&gt;
</content>
</entry>
<entry>
<title>selftests/rseq: Use rseq_unqual_scalar_typeof in macros</title>
<updated>2023-08-08T20:42:12Z</updated>
<author>
<name>Mathieu Desnoyers</name>
<email>mathieu.desnoyers@efficios.com</email>
</author>
<published>2023-06-27T15:29:23Z</published>
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<id>urn:sha1:2b2fe6052dd01fdb4e9a31031c2c9d8f03cf7753</id>
<content type='text'>
Use rseq_unqual_scalar_typeof() rather than typeof() in macros to remove
the volatile qualifier (if there is one in the input argument), thus
generating better assembly code in those scenarios.

Also add extra brackets around the "p" parameter in RSEQ_READ_ONCE(),
RSEQ_WRITE_ONCE(), and rseq_unqual_scalar_typeof() across architectures
to preserve expectations of operator priority. Here is an example that
shows how operator priority may be an issue with missing parentheses:

    #define m(p) \
    do { \
            __typeof__(*p) v = 0; \
    } while (0)

    void fct(unsigned long long *p1)
    {
            m(p1 + 1);      /* works */
            m(1 + p1);      /* broken */
    }

Signed-off-by: Mathieu Desnoyers &lt;mathieu.desnoyers@efficios.com&gt;
Cc: Peter Zijlstra &lt;peterz@infradead.org&gt;
Signed-off-by: Shuah Khan &lt;skhan@linuxfoundation.org&gt;
</content>
</entry>
<entry>
<title>selftests/rseq: riscv: Template memory ordering and percpu access mode</title>
<updated>2022-12-27T11:52:14Z</updated>
<author>
<name>Mathieu Desnoyers</name>
<email>mathieu.desnoyers@efficios.com</email>
</author>
<published>2022-11-22T20:39:19Z</published>
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<id>urn:sha1:171586a6ab66fb6be064e399ac2024ab459dfcf9</id>
<content type='text'>
Introduce a rseq-riscv-bits.h template header which is internally included
to generate the static inline functions covering:

- relaxed and release memory ordering,
- per-cpu-id and per-mm-cid per-cpu data access.

Signed-off-by: Mathieu Desnoyers &lt;mathieu.desnoyers@efficios.com&gt;
Signed-off-by: Peter Zijlstra (Intel) &lt;peterz@infradead.org&gt;
Link: https://lore.kernel.org/r/20221122203932.231377-18-mathieu.desnoyers@efficios.com
</content>
</entry>
<entry>
<title>selftests/rseq: Remove RSEQ_SKIP_FASTPATH code</title>
<updated>2022-12-27T11:52:12Z</updated>
<author>
<name>Mathieu Desnoyers</name>
<email>mathieu.desnoyers@efficios.com</email>
</author>
<published>2022-11-22T20:39:11Z</published>
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<id>urn:sha1:72cb1d7f2faca4fba81ab8417367d63852cd490c</id>
<content type='text'>
This code is not currently build by the test Makefile, adds complexity,
and is not overall useful considering that the abort handling loops to
retry the fast-path.

Signed-off-by: Mathieu Desnoyers &lt;mathieu.desnoyers@efficios.com&gt;
Signed-off-by: Peter Zijlstra (Intel) &lt;peterz@infradead.org&gt;
Link: https://lore.kernel.org/r/20221122203932.231377-10-mathieu.desnoyers@efficios.com
</content>
</entry>
<entry>
<title>selftests/rseq: riscv: fix 'literal-suffix' warning</title>
<updated>2022-06-28T07:08:28Z</updated>
<author>
<name>Michael Jeanson</name>
<email>mjeanson@efficios.com</email>
</author>
<published>2022-06-14T15:48:29Z</published>
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<id>urn:sha1:d47c0cc94a86b9098930523a9e68180bef6b26cf</id>
<content type='text'>
This header is also used in librseq where it can be included in C++
code, add a space between literals and string macros.

Signed-off-by: Michael Jeanson &lt;mjeanson@efficios.com&gt;
Signed-off-by: Peter Zijlstra (Intel) &lt;peterz@infradead.org&gt;
Reviewed-by: Mathieu Desnoyers &lt;mathieu.desnoyers@efficios.com&gt;
Link: https://lore.kernel.org/r/20220614154830.1367382-3-mjeanson@efficios.com
</content>
</entry>
<entry>
<title>selftests/rseq: riscv: use rseq_get_abi() helper</title>
<updated>2022-06-28T07:08:28Z</updated>
<author>
<name>Michael Jeanson</name>
<email>mjeanson@efficios.com</email>
</author>
<published>2022-06-14T15:48:28Z</published>
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<id>urn:sha1:4f3394924358fe04ced0411c72fc7eeb0d3be652</id>
<content type='text'>
Make the RISC-V rseq selftests compatible with glibc-2.35 by using the
rseq_get_abi() helper.

Signed-off-by: Michael Jeanson &lt;mjeanson@efficios.com&gt;
Signed-off-by: Peter Zijlstra (Intel) &lt;peterz@infradead.org&gt;
Reviewed-by: Mathieu Desnoyers &lt;mathieu.desnoyers@efficios.com&gt;
Link: https://lore.kernel.org/r/20220614154830.1367382-2-mjeanson@efficios.com
</content>
</entry>
<entry>
<title>rseq/selftests: Add support for RISC-V</title>
<updated>2022-03-22T21:45:19Z</updated>
<author>
<name>Vincent Chen</name>
<email>vincent.chen@sifive.com</email>
</author>
<published>2022-03-08T08:32:53Z</published>
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<id>urn:sha1:6d1a6f464efd596779d1b272b3dc8170c5fa189f</id>
<content type='text'>
Add support for RISC-V in the rseq selftests, which covers both
64-bit and 32-bit ISA with little endian mode.

Signed-off-by: Vincent Chen &lt;vincent.chen@sifive.com&gt;
Tested-by: Eric Lin &lt;eric.lin@sifive.com&gt;
Reviewed-by: Mathieu Desnoyers &lt;mathieu.desnoyers@efficios.com&gt;
Signed-off-by: Palmer Dabbelt &lt;palmer@rivosinc.com&gt;
</content>
</entry>
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