kernel/sound/soc/sof/intel/tgl.c, branch linux-6.2.y

ASoC: SOF: Intel: pci-tgl: unblock S5 entry if DMA stop has failed"

2022-12-12T15:44:20Z

If system shutdown has not been completed cleanly, it is possible the DMA stream shutdown has not been done, or was not clean. If this is the case, Intel TGL/ADL HDA platforms may fail to shutdown cleanly due to pending HDA DMA transactions. To avoid this, detect this scenario in the shutdown callback, and perform an additional controller reset. This has been tested to unblock S5 entry if this condition is hit. Co-developed-by: Archana Patni Signed-off-by: Archana Patni Signed-off-by: Kai Vehmanen Reviewed-by: Pierre-Louis Bossart Reviewed-by: Péter Ujfalusi Reviewed-by: Ranjani Sridharan Link: https://lore.kernel.org/r/20221209114529.3909192-2-kai.vehmanen@linux.intel.com Signed-off-by: Mark Brown

ASoC: SOF: Intel: hda: add callback to check SoundWire lcount information

2022-11-23T15:32:05Z

The number of links is stored in different registers depending on the IP version, add sdw_check_lcount() callback. This callback only checks that the number of links supported in hardware is compatible with the number of links exposed in ACPI _DSD properties. Signed-off-by: Pierre-Louis Bossart Reviewed-by: Péter Ujfalusi Reviewed-by: Ranjani Sridharan Signed-off-by: Bard Liao Link: https://lore.kernel.org/r/20221111042653.45520-6-yung-chuan.liao@linux.intel.com Signed-off-by: Mark Brown

ASoC: SOF: Intel: hda: add per-chip enable_sdw_irq() callback

2022-11-23T15:32:02Z

Different generations of Intel hardware rely on different programming sequences to enable SoundWire IP. In existing hardware, the SoundWire interrupt is enabled with a register field in the DSP register space. With HDaudio multi-link extensions registers, the SoundWire interrupt will be enabled with a generic interrupt enable field in LCTL, without any dependency on the DSP being enabled. Add a per-chip callback following the example of the check_sdw_irq() model already upstream. Note that the callback is not populated yet for MeteorLake (MTL) since the interrupts are already enabled in the init. A follow-up patch will move the functionality to this callback after a couple of cleanups. Signed-off-by: Pierre-Louis Bossart Reviewed-by: Péter Ujfalusi Reviewed-by: Ranjani Sridharan Signed-off-by: Bard Liao Link: https://lore.kernel.org/r/20221111042653.45520-3-yung-chuan.liao@linux.intel.com Signed-off-by: Mark Brown

ASoC: SOF: Intel: add d0i3_offset in chip_info

2022-11-07T17:10:07Z

MTL has different d0i3 offset compared to cavs platforms. Use d0i3_offset to unify the setting. Reviewed-by: Ranjani Sridharan Signed-off-by: Rander Wang Signed-off-by: Pierre-Louis Bossart Link: https://lore.kernel.org/r/20221107164154.21925-3-pierre-louis.bossart@linux.intel.com Signed-off-by: Mark Brown

ASoC: SOF: Intel: Add ipc4 library loading implementation

2022-10-21T12:05:07Z

On Intel HDA platforms the library loading is done via DMA and an IPC message is also need to be sent to initiate the downloading of the new library. Co-developed-by: Ranjani Sridharan Signed-off-by: Ranjani Sridharan Signed-off-by: Peter Ujfalusi Reviewed-by: Ranjani Sridharan Reviewed-by: Pierre-Louis Bossart Reviewed-by: Chao Song Reviewed-by: Kai Vehmanen Link: https://lore.kernel.org/r/20221020121238.18339-16-peter.ujfalusi@linux.intel.com Signed-off-by: Mark Brown

ASoC: SOF: ipc4/Intel: Improve and enable IPC error dump

2022-09-23T19:46:25Z

Merge series from Peter Ujfalusi : On Intel platforms the registers for DSP communications are used differently, the IPC dump information is not correct since important registers are not printed and existing ones are used a bit differently for IPC4. As a last step, enable the IPC timeout 'handling' and allow the printout of the now usefull IPC dump.

ASoC: SOF: Intel: cnl: Add separate ops for ipc_dump for IPC4

2022-09-23T13:53:17Z

The use of the IPC registers are different between IPC3 and IPC4. The ipc_dump needs to use different prints depending on the used IPC protocol. Signed-off-by: Peter Ujfalusi Reviewed-by: Ranjani Sridharan Reviewed-by: Kai Vehmanen Reviewed-by: Rander Wang Link: https://lore.kernel.org/r/20220923133616.26267-2-peter.ujfalusi@linux.intel.com Signed-off-by: Mark Brown

ASoC: SOF: Intel: define and set the disable_interrupts op for cavs platforms

2022-09-23T12:56:17Z

Disable the IPC and SDW nterrupts in the disable_interrupts op for cavs platforms. Signed-off-by: Ranjani Sridharan Reviewed-by: Bard Liao Reviewed-by: Rander Wang Reviewed-by: Pierre-Louis Bossart Link: https://lore.kernel.org/r/20220922213644.666315-7-ranjani.sridharan@linux.intel.com Signed-off-by: Mark Brown

ASoC: SOF: Intel: define and set power_down_dsp op for HDA platforms

2022-09-23T12:56:13Z

hda_power_down_dsp is set for power_down_dsp op for all HDA platforms. Signed-off-by: Fred Oh Reviewed-by: Rander Wang Reviewed-by: Bard Liao Signed-off-by: Ranjani Sridharan Link: https://lore.kernel.org/r/20220922213644.666315-3-ranjani.sridharan@linux.intel.com Signed-off-by: Mark Brown

ASoC: SOF: Intel: hda: refine SSP count support

2022-09-19T17:11:44Z

The SSP count is incorrect for TGL and MTL devices, the SSP count is limited to 3 (I2SPC parameter in the Integration HAS). Signed-off-by: Pierre-Louis Bossart Reviewed-by: Bard Liao Reviewed-by: Péter Ujfalusi Link: https://lore.kernel.org/r/20220919115350.43104-2-pierre-louis.bossart@linux.intel.com Signed-off-by: Mark Brown