<feed xmlns='http://www.w3.org/2005/Atom'>
<title>kernel/sound/soc/sof/amd, branch linux-6.2.y</title>
<subtitle>Hosts the 0x221E linux distro kernel.</subtitle>
<id>https://universe.0xinfinity.dev/distro/kernel/atom?h=linux-6.2.y</id>
<link rel='self' href='https://universe.0xinfinity.dev/distro/kernel/atom?h=linux-6.2.y'/>
<link rel='alternate' type='text/html' href='https://universe.0xinfinity.dev/distro/kernel/'/>
<updated>2023-02-02T15:37:28Z</updated>
<entry>
<title>ASoC: SOF: amd: Fix for handling spurious interrupts from DSP</title>
<updated>2023-02-02T15:37:28Z</updated>
<author>
<name>V sujith kumar Reddy</name>
<email>Vsujithkumar.Reddy@amd.com</email>
</author>
<published>2023-02-03T12:32:52Z</published>
<link rel='alternate' type='text/html' href='https://universe.0xinfinity.dev/distro/kernel/commit/?id=2e7c6652f9b86c01cbd4e988057a746a3a461969'/>
<id>urn:sha1:2e7c6652f9b86c01cbd4e988057a746a3a461969</id>
<content type='text'>
As interrupts are Level-triggered,unless and until we deassert the register
the interrupts are generated which causes spurious interrupts unhandled.

Now we deasserted the interrupt at top half which solved the below
"nobody cared" warning.

warning reported in dmesg:
	irq 80: nobody cared (try booting with the "irqpoll" option)
	CPU: 5 PID: 2735 Comm: irq/80-AudioDSP
		Not tainted 5.15.86-15817-g4c19f3e06d49 #1 1bd3fd932cf58caacc95b0504d6ea1e3eab22289
	Hardware name: Google Skyrim/Skyrim, BIOS Google_Skyrim.15303.0.0 01/03/2023
	Call Trace:
	&lt;IRQ&gt;
	dump_stack_lvl+0x69/0x97
	 __report_bad_irq+0x3a/0xae
	note_interrupt+0x1a9/0x1e3
	handle_irq_event_percpu+0x4b/0x6e
	handle_irq_event+0x36/0x5b
	handle_fasteoi_irq+0xae/0x171
	 __common_interrupt+0x48/0xc4
	&lt;/IRQ&gt;

	handlers:
	acp_irq_handler [snd_sof_amd_acp] threaded [&lt;000000007e089f34&gt;] acp_irq_thread [snd_sof_amd_acp]
	Disabling IRQ #80

Signed-off-by: V sujith kumar Reddy &lt;Vsujithkumar.Reddy@amd.com&gt;
Link: https://lore.kernel.org/r/20230203123254.1898794-1-Vsujithkumar.Reddy@amd.com
Signed-off-by: Mark Brown &lt;broonie@kernel.org&gt;
</content>
</entry>
<entry>
<title>ASoC : SOF: amd: Add support for IPC and DSP dumps</title>
<updated>2022-12-05T14:05:37Z</updated>
<author>
<name>V sujith kumar Reddy</name>
<email>Vsujithkumar.Reddy@amd.com</email>
</author>
<published>2022-12-05T12:06:49Z</published>
<link rel='alternate' type='text/html' href='https://universe.0xinfinity.dev/distro/kernel/commit/?id=41cfad23b5ebef2dbddecff2ddeb27ca973f98a8'/>
<id>urn:sha1:41cfad23b5ebef2dbddecff2ddeb27ca973f98a8</id>
<content type='text'>
Add support for IPC and DSP dumps for AMD platforms.

Signed-off-by: V sujith kumar Reddy &lt;Vsujithkumar.Reddy@amd.com&gt;
Link: https://lore.kernel.org/r/20221205120649.1950576-3-Vsujithkumar.Reddy@amd.com
Signed-off-by: Mark Brown &lt;broonie@kernel.org&gt;
</content>
</entry>
<entry>
<title>ASoC: SOF: amd: Use poll function instead to read ACP_SHA_DSP_FW_QUALIFIER</title>
<updated>2022-12-05T14:05:36Z</updated>
<author>
<name>Ajye Huang</name>
<email>ajye_huang@compal.corp-partner.google.com</email>
</author>
<published>2022-12-05T12:06:48Z</published>
<link rel='alternate' type='text/html' href='https://universe.0xinfinity.dev/distro/kernel/commit/?id=2a2f5f2384b9791a028901aac3f49c488839d073'/>
<id>urn:sha1:2a2f5f2384b9791a028901aac3f49c488839d073</id>
<content type='text'>
The Skyrim project and Whiterun met error when DSP
loading during device boot.
Ex, error in kernel log,
ERR kernel: [   16.124537] snd_sof_amd_rembrandt
0000:04:00.5: PSP validation failed.

Use the snd_sof_dsp_read_poll_timeout function to successfully
read the FW_QUALIFIER register

Signed-off-by: Ajye Huang &lt;ajye_huang@compal.corp-partner.google.com&gt;
Signed-off-by: V sujith kumar Reddy &lt;Vsujithkumar.Reddy@amd.com&gt;
Link: https://lore.kernel.org/r/20221205120649.1950576-2-Vsujithkumar.Reddy@amd.com
Signed-off-by: Mark Brown &lt;broonie@kernel.org&gt;
</content>
</entry>
<entry>
<title>ASoC: SOF: amd: ADD HS and SP virtual DAI.</title>
<updated>2022-11-28T13:04:22Z</updated>
<author>
<name>V sujith kumar Reddy</name>
<email>Vsujithkumar.Reddy@amd.com</email>
</author>
<published>2022-11-23T12:19:10Z</published>
<link rel='alternate' type='text/html' href='https://universe.0xinfinity.dev/distro/kernel/commit/?id=9fd3b5b11db2fbbf0438324696de8233c0a78dad'/>
<id>urn:sha1:9fd3b5b11db2fbbf0438324696de8233c0a78dad</id>
<content type='text'>
ADD HS and SP virtual DAI driver to support AMD platforms.

Signed-off-by: V sujith kumar Reddy &lt;Vsujithkumar.Reddy@amd.com&gt;
Link: https://lore.kernel.org/r/20221123121911.3446224-4-vsujithkumar.reddy@amd.corp-partner.google.com
Signed-off-by: Mark Brown &lt;broonie@kernel.org&gt;
</content>
</entry>
<entry>
<title>ASoC: SOF: amd: Fix for selecting clock source as external clock.</title>
<updated>2022-11-28T13:04:21Z</updated>
<author>
<name>V sujith kumar Reddy</name>
<email>Vsujithkumar.Reddy@amd.com</email>
</author>
<published>2022-11-23T12:19:09Z</published>
<link rel='alternate' type='text/html' href='https://universe.0xinfinity.dev/distro/kernel/commit/?id=f9ced7dbbb551885c63632f1594997bdaf2177ee'/>
<id>urn:sha1:f9ced7dbbb551885c63632f1594997bdaf2177ee</id>
<content type='text'>
By default clock source is selected as internal clock of 96Mhz
which is not configurable. Now we select the clock source to
external clock (ACLK) which can be configurable to different clock
ranges depending on usecase.

Signed-off-by: V sujith kumar Reddy &lt;Vsujithkumar.Reddy@amd.com&gt;
Link: https://lore.kernel.org/r/20221123121911.3446224-3-vsujithkumar.reddy@amd.corp-partner.google.com
Signed-off-by: Mark Brown &lt;broonie@kernel.org&gt;
</content>
</entry>
<entry>
<title>ASoC: SOF: amd: Fix for reading position updates from stream box.</title>
<updated>2022-11-28T13:04:20Z</updated>
<author>
<name>V sujith kumar Reddy</name>
<email>Vsujithkumar.Reddy@amd.com</email>
</author>
<published>2022-11-23T12:19:08Z</published>
<link rel='alternate' type='text/html' href='https://universe.0xinfinity.dev/distro/kernel/commit/?id=aae7e412b0ec0378e392b18c50b612dae09cdb74'/>
<id>urn:sha1:aae7e412b0ec0378e392b18c50b612dae09cdb74</id>
<content type='text'>
By default the position updates are read from dsp box when streambox
size is not defined.if the streambox size is defined to some value
then position updates can be read from the streambox.

Signed-off-by: V sujith kumar Reddy &lt;Vsujithkumar.Reddy@amd.com&gt;
Link: https://lore.kernel.org/r/20221123121911.3446224-2-vsujithkumar.reddy@amd.corp-partner.google.com
Signed-off-by: Mark Brown &lt;broonie@kernel.org&gt;
</content>
</entry>
<entry>
<title>ASoC: SOF: amd: Use the basefw firmware container directly</title>
<updated>2022-10-21T12:04:55Z</updated>
<author>
<name>Peter Ujfalusi</name>
<email>peter.ujfalusi@linux.intel.com</email>
</author>
<published>2022-10-20T12:12:22Z</published>
<link rel='alternate' type='text/html' href='https://universe.0xinfinity.dev/distro/kernel/commit/?id=b9bed09aa97f90a40695eb472b1baba81242e3ed'/>
<id>urn:sha1:b9bed09aa97f90a40695eb472b1baba81242e3ed</id>
<content type='text'>
Switch to access to the firmware struct via sdev-&gt;basefw container to
unblock the removal of the firmware information from plat_data.

Signed-off-by: Peter Ujfalusi &lt;peter.ujfalusi@linux.intel.com&gt;
Reviewed-by: Ranjani Sridharan &lt;ranjani.sridharan@linux.intel.com&gt;
Reviewed-by: Pierre-Louis Bossart &lt;pierre-louis.bossart@linux.intel.com&gt;
Reviewed-by: Chao Song &lt;chao.song@intel.com&gt;
Reviewed-by: Kai Vehmanen &lt;kai.vehmanen@linux.intel.com&gt;
Link: https://lore.kernel.org/r/20221020121238.18339-4-peter.ujfalusi@linux.intel.com
Signed-off-by: Mark Brown &lt;broonie@kernel.org&gt;
</content>
</entry>
<entry>
<title>ASoC: SOF: amd: increase SRAM inbox and outbox size to 1024</title>
<updated>2022-09-20T18:38:04Z</updated>
<author>
<name>V sujith kumar Reddy</name>
<email>Vsujithkumar.Reddy@amd.com</email>
</author>
<published>2022-09-13T14:43:18Z</published>
<link rel='alternate' type='text/html' href='https://universe.0xinfinity.dev/distro/kernel/commit/?id=40d3c041e2f871b3d2d78c8e360224f788ac17ab'/>
<id>urn:sha1:40d3c041e2f871b3d2d78c8e360224f788ac17ab</id>
<content type='text'>
Increase inbox and outbox mailbox size from 512 to 1024 to
support thirdparty DTS integration ipc tx/rx messages communication.
This is done through firmware window get info.

Signed-off-by: V sujith kumar Reddy &lt;Vsujithkumar.Reddy@amd.com&gt;
Reviewed-by: Pierre-Louis Bossart &lt;pierre-louis.bossart@linux.intel.com&gt;
Link: https://lore.kernel.org/r/20220913144319.1055302-5-Vsujithkumar.Reddy@amd.com
Signed-off-by: Mark Brown &lt;broonie@kernel.org&gt;
</content>
</entry>
<entry>
<title>ASoC: SOF: amd: Add support for Rembrandt plaform.</title>
<updated>2022-09-20T18:38:02Z</updated>
<author>
<name>V sujith kumar Reddy</name>
<email>Vsujithkumar.Reddy@amd.com</email>
</author>
<published>2022-09-13T14:43:16Z</published>
<link rel='alternate' type='text/html' href='https://universe.0xinfinity.dev/distro/kernel/commit/?id=41cb85bc4b526bb228579c04857bc58213e5f9b5'/>
<id>urn:sha1:41cb85bc4b526bb228579c04857bc58213e5f9b5</id>
<content type='text'>
Add pci driver and platform driver to enable SOF support on ACP6x
architecture based Rembrandt platform.

Signed-off-by: Ajit Kumar Pandey &lt;AjitKumar.Pandey@amd.com&gt;
Signed-off-by: V sujith kumar Reddy &lt;Vsujithkumar.Reddy@amd.com&gt;
Reviewed-by: Pierre-Louis Bossart &lt;pierre-louis.bossart@linux.intel.com&gt;
Link: https://lore.kernel.org/r/20220913144319.1055302-3-Vsujithkumar.Reddy@amd.com
Signed-off-by: Mark Brown &lt;broonie@kernel.org&gt;
</content>
</entry>
<entry>
<title>ASoC: SOF: amd: Make ACP core code generic for newer SOC transition</title>
<updated>2022-09-20T18:38:01Z</updated>
<author>
<name>Ajit Kumar Pandey</name>
<email>AjitKumar.Pandey@amd.com</email>
</author>
<published>2022-09-13T14:43:15Z</published>
<link rel='alternate' type='text/html' href='https://universe.0xinfinity.dev/distro/kernel/commit/?id=4da6b033f5454ccbac2d5795d7edfb3f2a777104'/>
<id>urn:sha1:4da6b033f5454ccbac2d5795d7edfb3f2a777104</id>
<content type='text'>
Newer AMD SOC differs slightly in terms of few registers offset and
configuration. Add offsets into chip_info struct to make core ACP
code more generic and resusable on newer SOC.

Signed-off-by: Ajit Kumar Pandey &lt;AjitKumar.Pandey@amd.com&gt;
Signed-off-by: V sujith kumar Reddy &lt;Vsujithkumar.Reddy@amd.com&gt;
Reviewed-by: Pierre-Louis Bossart &lt;pierre-louis.bossart@linux.intel.com&gt;
Link: https://lore.kernel.org/r/20220913144319.1055302-2-Vsujithkumar.Reddy@amd.com
Signed-off-by: Mark Brown &lt;broonie@kernel.org&gt;
</content>
</entry>
</feed>
