kernel/sound/soc/sof/amd/acp.c, branch linux-6.2.y

ASoC: SOF: amd: Fix for handling spurious interrupts from DSP

2023-02-02T15:37:28Z

As interrupts are Level-triggered,unless and until we deassert the register the interrupts are generated which causes spurious interrupts unhandled. Now we deasserted the interrupt at top half which solved the below "nobody cared" warning. warning reported in dmesg: irq 80: nobody cared (try booting with the "irqpoll" option) CPU: 5 PID: 2735 Comm: irq/80-AudioDSP Not tainted 5.15.86-15817-g4c19f3e06d49 #1 1bd3fd932cf58caacc95b0504d6ea1e3eab22289 Hardware name: Google Skyrim/Skyrim, BIOS Google_Skyrim.15303.0.0 01/03/2023 Call Trace: dump_stack_lvl+0x69/0x97 __report_bad_irq+0x3a/0xae note_interrupt+0x1a9/0x1e3 handle_irq_event_percpu+0x4b/0x6e handle_irq_event+0x36/0x5b handle_fasteoi_irq+0xae/0x171 __common_interrupt+0x48/0xc4 handlers: acp_irq_handler [snd_sof_amd_acp] threaded [<000000007e089f34>] acp_irq_thread [snd_sof_amd_acp] Disabling IRQ #80 Signed-off-by: V sujith kumar Reddy Link: https://lore.kernel.org/r/20230203123254.1898794-1-Vsujithkumar.Reddy@amd.com Signed-off-by: Mark Brown

ASoC: SOF: amd: Use poll function instead to read ACP_SHA_DSP_FW_QUALIFIER

2022-12-05T14:05:36Z

The Skyrim project and Whiterun met error when DSP loading during device boot. Ex, error in kernel log, ERR kernel: [ 16.124537] snd_sof_amd_rembrandt 0000:04:00.5: PSP validation failed. Use the snd_sof_dsp_read_poll_timeout function to successfully read the FW_QUALIFIER register Signed-off-by: Ajye Huang Signed-off-by: V sujith kumar Reddy Link: https://lore.kernel.org/r/20221205120649.1950576-2-Vsujithkumar.Reddy@amd.com Signed-off-by: Mark Brown

ASoC: SOF: amd: Fix for selecting clock source as external clock.

2022-11-28T13:04:21Z

By default clock source is selected as internal clock of 96Mhz which is not configurable. Now we select the clock source to external clock (ACLK) which can be configurable to different clock ranges depending on usecase. Signed-off-by: V sujith kumar Reddy Link: https://lore.kernel.org/r/20221123121911.3446224-3-vsujithkumar.reddy@amd.corp-partner.google.com Signed-off-by: Mark Brown

ASoC: SOF: amd: increase SRAM inbox and outbox size to 1024

2022-09-20T18:38:04Z

Increase inbox and outbox mailbox size from 512 to 1024 to support thirdparty DTS integration ipc tx/rx messages communication. This is done through firmware window get info. Signed-off-by: V sujith kumar Reddy Reviewed-by: Pierre-Louis Bossart Link: https://lore.kernel.org/r/20220913144319.1055302-5-Vsujithkumar.Reddy@amd.com Signed-off-by: Mark Brown

ASoC: SOF: amd: Make ACP core code generic for newer SOC transition

2022-09-20T18:38:01Z

Newer AMD SOC differs slightly in terms of few registers offset and configuration. Add offsets into chip_info struct to make core ACP code more generic and resusable on newer SOC. Signed-off-by: Ajit Kumar Pandey Signed-off-by: V sujith kumar Reddy Reviewed-by: Pierre-Louis Bossart Link: https://lore.kernel.org/r/20220913144319.1055302-2-Vsujithkumar.Reddy@amd.com Signed-off-by: Mark Brown

ASoC: SOF: amd: Add SOF pm ops callback for Renoir

2022-06-06T21:08:21Z

Add SOF PM ops callback in renoir dsp ops to power off and on ACP IP block during system suspend and resume on Renoir platform. Signed-off-by: Ajit Kumar Pandey Signed-off-by: Pierre-Louis Bossart Link: https://lore.kernel.org/r/20220606210212.146626-2-pierre-louis.bossart@linux.intel.com Signed-off-by: Mark Brown

ASoC: SOF: amd: Use dedicated MBOX for ACP and PSP communication

2022-04-21T17:25:18Z

We are currently using generic PSP Mailbox register for sending SHA complete command to PSP but observe random arbitration issue during PSP validation as MP0_C2PMSG_26_REG used by other kernel modules. Use separate mailbox registers and doorbell mechanism to send SHA_DMA complete command to PSP. This fixes such validation issues and added flexibility for sending more ACP commands to PSP in future as new mbox registers i.e MP0_C2PMSG_114_REG and MP0_C2PMSG_73_REG are dedicated by PSP for ACP communications. Reviewed-by: Ranjani Sridharan Reviewed-by: Bard Liao Signed-off-by: Ajit Kumar Pandey Signed-off-by: Pierre-Louis Bossart Link: https://lore.kernel.org/r/20220421165820.337207-3-pierre-louis.bossart@linux.intel.com Signed-off-by: Mark Brown

ASoC: SOF: amd: Add psp_mbox_ready() and psp_send_cmd() callback

2022-04-21T17:25:17Z

We need to ensure if PSP is mbox ready before and after sending cmd to PSP over SMN interface. Add method to check MBOX_READY bit of PSP with some delay over ACP_PSP_TIMEOUT_COUNTER. Replace psp_fw_validate with new method psp_send_cmd() to send command via psp mailbox. Reviewed-by: Ranjani Sridharan Signed-off-by: Ajit Kumar Pandey Signed-off-by: Pierre-Louis Bossart Link: https://lore.kernel.org/r/20220421165820.337207-2-pierre-louis.bossart@linux.intel.com Signed-off-by: Mark Brown

ASoC: SOF: amd: Remove unneeded semicolon

2022-03-09T17:34:56Z

Fix the following coccicheck warnings: ./sound/soc/sof/amd/acp.c:280:3-4: Unneeded semicolon. Reported-by: Abaci Robot Signed-off-by: Jiapeng Chong Link: https://lore.kernel.org/r/20220309004929.125558-2-jiapeng.chong@linux.alibaba.com Signed-off-by: Mark Brown

ASoC: SOF: amd: Move group register configuration to acp-loader

2022-03-07T13:12:50Z

We are using PTE_GRP1 for DMA operations to load firmware binaries but we are enabling PTE_GRP and flushing ATU cache much before in probe callbacks. This can cause issue if we try to load firmware runtime during system resume as probe callback will not be invoked hence PTE_GRP will not be enabled. Moreover it makes more sense to flush the cache after register configuration. Move PTE group register configuration to acp-loader within pre_fw_run callback to avoid such issue. Reviewed-by: Ranjani Sridharan Signed-off-by: Ajit Kumar Pandey Signed-off-by: Pierre-Louis Bossart Link: https://lore.kernel.org/r/20220304205733.62233-7-pierre-louis.bossart@linux.intel.com Signed-off-by: Mark Brown