<feed xmlns='http://www.w3.org/2005/Atom'>
<title>kernel/include/video/imx-ipu-v3.h, branch linux-4.16.y</title>
<subtitle>Hosts the 0x221E linux distro kernel.</subtitle>
<id>https://universe.0xinfinity.dev/distro/kernel/atom?h=linux-4.16.y</id>
<link rel='self' href='https://universe.0xinfinity.dev/distro/kernel/atom?h=linux-4.16.y'/>
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<updated>2017-12-19T11:49:11Z</updated>
<entry>
<title>gpu: ipu-v3: prg: add modifier support</title>
<updated>2017-12-19T11:49:11Z</updated>
<author>
<name>Lucas Stach</name>
<email>l.stach@pengutronix.de</email>
</author>
<published>2017-11-10T16:09:59Z</published>
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<id>urn:sha1:a2ceec52d9a48bd046e5496e266dda1c57872f4b</id>
<content type='text'>
Allow to pass through the modifier to the PRE unit and extend the
format check with the supported modifiers.

Signed-off-by: Lucas Stach &lt;l.stach@pengutronix.de&gt;
Signed-off-by: Philipp Zabel &lt;p.zabel@pengutronix.de&gt;
</content>
</entry>
<entry>
<title>gpu: ipu-v3: Add support for double read/write reduction</title>
<updated>2017-06-08T06:57:18Z</updated>
<author>
<name>Philipp Zabel</name>
<email>p.zabel@pengutronix.de</email>
</author>
<published>2014-09-17T13:44:54Z</published>
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<id>urn:sha1:e1e9733cd37908a9ba61e29154561f0c81420e06</id>
<content type='text'>
Allow to skip writing odd chroma rows by setting the RDRW bit for
4:2:0 chroma subsampled formats for any IDMAC write channel. This
also allows to skip reading odd rows for the VDIC read channel.

Signed-off-by: Philipp Zabel &lt;p.zabel@pengutronix.de&gt;
</content>
</entry>
<entry>
<title>gpu: ipu-v3: add driver for Prefetch Resolve Gasket</title>
<updated>2017-03-16T09:14:02Z</updated>
<author>
<name>Lucas Stach</name>
<email>l.stach@pengutronix.de</email>
</author>
<published>2017-03-08T11:13:16Z</published>
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<id>urn:sha1:ea9c260514c15f14d43a4c099646c44238dccf1e</id>
<content type='text'>
This adds support for the i.MX6 QUadPlus PRG unit. It glues together the
IPU and the PRE units.

Signed-off-by: Lucas Stach &lt;l.stach@pengutronix.de&gt;
Signed-off-by: Philipp Zabel &lt;p.zabel@pengutronix.de&gt;
---
v4: add missing ipu_soc-&gt;prg_priv
</content>
</entry>
<entry>
<title>gpu: ipu-v3: add support for separate alpha channels</title>
<updated>2017-03-15T14:42:31Z</updated>
<author>
<name>Philipp Zabel</name>
<email>p.zabel@pengutronix.de</email>
</author>
<published>2015-01-09T10:03:13Z</published>
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<id>urn:sha1:e72db3b1e50febff493bc5e3fb57da9cb8cc3d91</id>
<content type='text'>
The IPUv3 can read 8-bit alpha values from a separate IDMAC channel driven
by the Alpha Transparency Controller (ATC) for the graphics IDMAC channels.
This allows to reduce memory bandwidth via a conditional read mechanism or
to support planar YUV formats with alpha transparency.

Signed-off-by: Philipp Zabel &lt;p.zabel@pengutronix.de&gt;
</content>
</entry>
<entry>
<title>gpu: ipu-v3: add unsynchronised DP channel disabling</title>
<updated>2017-03-15T14:28:27Z</updated>
<author>
<name>Philipp Zabel</name>
<email>p.zabel@pengutronix.de</email>
</author>
<published>2017-02-24T17:23:55Z</published>
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<id>urn:sha1:f9bb7acb9b19a40dbd9d1b89380335dc8e23925f</id>
<content type='text'>
When disabling the foreground DP channel during a modeset, the DC is
already disabled without waiting for end of frame. There is no reason
to wait for a frame boundary before updating the DP registers in that
case.
Add support to apply updates immediately. No functional changes, yet.

Signed-off-by: Philipp Zabel &lt;p.zabel@pengutronix.de&gt;
Reviewed-by: Lucas Stach &lt;l.stach@pengutronix.de&gt;
</content>
</entry>
<entry>
<title>gpu: ipu-v3: add ipu_csi_set_downsize</title>
<updated>2016-11-07T14:17:47Z</updated>
<author>
<name>Philipp Zabel</name>
<email>p.zabel@pengutronix.de</email>
</author>
<published>2016-10-05T15:33:45Z</published>
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<id>urn:sha1:867341b95891ca176e9cb5fcc3c68b325f0eb306</id>
<content type='text'>
Support downsizing to 1/2 width and/or height in the CSI.

Signed-off-by: Philipp Zabel &lt;p.zabel@pengutronix.de&gt;
</content>
</entry>
<entry>
<title>gpu: ipu-cpmem: remove unused ipu_cpmem_set_yuv_planar function</title>
<updated>2016-10-20T12:40:02Z</updated>
<author>
<name>Philipp Zabel</name>
<email>p.zabel@pengutronix.de</email>
</author>
<published>2016-10-18T11:33:31Z</published>
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<id>urn:sha1:9c24d680de0d7b68ac4c07cc685d9dbf83751a1d</id>
<content type='text'>
ipu_cpmem_set_yuv_planar_full is only used directly, remove the wrapper.

Suggested-by: Liu Ying &lt;gnuiyl@gmail.com&gt;
Signed-off-by: Philipp Zabel &lt;p.zabel@pengutronix.de&gt;
Acked-by: Liu Ying &lt;gnuiyl@gmail.com&gt;
</content>
</entry>
<entry>
<title>gpu: ipu-v3: Add ipu_rot_mode_is_irt()</title>
<updated>2016-09-19T06:30:14Z</updated>
<author>
<name>Steve Longerbeam</name>
<email>slongerbeam@gmail.com</email>
</author>
<published>2016-09-17T19:33:57Z</published>
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<id>urn:sha1:8b9c3d5099b265892ab3578bc757d9b81e5655a6</id>
<content type='text'>
Add a macro that returns boolean true if the given ipu_rotate_mode
requires the use of the Image Rotator.

Signed-off-by: Steve Longerbeam &lt;steve_longerbeam@mentor.com&gt;
Signed-off-by: Philipp Zabel &lt;p.zabel@pengutronix.de&gt;
</content>
</entry>
<entry>
<title>gpu: ipu-v3: Add FSU channel linking support</title>
<updated>2016-08-29T14:30:23Z</updated>
<author>
<name>Steve Longerbeam</name>
<email>slongerbeam@gmail.com</email>
</author>
<published>2016-08-18T00:50:17Z</published>
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<id>urn:sha1:ac4708fab1422905870a1c286e69d784ddc7358c</id>
<content type='text'>
Adds functions to link and unlink source channels to sink
channels in the FSU:

int ipu_fsu_link(struct ipu_soc *ipu, int src_ch, int sink_ch);
int ipu_fsu_unlink(struct ipu_soc *ipu, int src_ch, int sink_ch);

The channels numbers are usually IDMAC channels, but they can also be
channels that do not transfer data to or from memory. The following
convenience functions can be used in place of ipu_fsu_link/unlink()
when both source and sink channels are IDMAC channels:

int ipu_idmac_link(struct ipuv3_channel *src, struct ipuv3_channel *sink);
int ipu_idmac_unlink(struct ipuv3_channel *src, struct ipuv3_channel *sink);

So far the following links are supported:

IPUV3_CHANNEL_IC_PRP_ENC_MEM -&gt; IPUV3_CHANNEL_MEM_ROT_ENC
PUV3_CHANNEL_IC_PRP_VF_MEM   -&gt; IPUV3_CHANNEL_MEM_ROT_VF
IPUV3_CHANNEL_IC_PP_MEM      -&gt; IPUV3_CHANNEL_MEM_ROT_PP
IPUV3_CHANNEL_CSI_DIRECT     -&gt; IPUV3_CHANNEL_CSI_VDI_PREV

More links can be added to the fsu_link_info[] array.

Signed-off-by: Steve Longerbeam &lt;steve_longerbeam@mentor.com&gt;
Signed-off-by: Philipp Zabel &lt;p.zabel@pengutronix.de&gt;
</content>
</entry>
<entry>
<title>gpu: ipu-v3: Add Video Deinterlacer unit</title>
<updated>2016-08-29T14:30:11Z</updated>
<author>
<name>Steve Longerbeam</name>
<email>slongerbeam@gmail.com</email>
</author>
<published>2016-08-18T00:50:16Z</published>
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<id>urn:sha1:2d2ead4530771de0c5f2f7f0a7924deb045c4cce</id>
<content type='text'>
Adds the Video Deinterlacer (VDIC) unit.

Signed-off-by: Steve Longerbeam &lt;steve_longerbeam@mentor.com&gt;
Signed-off-by: Philipp Zabel &lt;p.zabel@pengutronix.de&gt;
</content>
</entry>
</feed>
