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<title>kernel/include/uapi/rdma/mlx5-abi.h, branch linux-5.2.y</title>
<subtitle>Hosts the 0x221E linux distro kernel.</subtitle>
<id>https://universe.0xinfinity.dev/distro/kernel/atom?h=linux-5.2.y</id>
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<updated>2019-04-25T13:33:00Z</updated>
<entry>
<title>Merge branch 'mlx5_tir_icm' into rdma.git for-next</title>
<updated>2019-04-25T13:33:00Z</updated>
<author>
<name>Jason Gunthorpe</name>
<email>jgg@mellanox.com</email>
</author>
<published>2019-04-25T13:26:02Z</published>
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<id>urn:sha1:1d045aa76fe8105cbb9fc0dfa1d15ae332551f25</id>
<content type='text'>
Ariel Levkovich says:

====================
The series exposes the ICM address of the receive transport
interface (TIR) of Raw Packet and RSS QPs to the user since they are
required to properly create and insert steering rules that direct flows to
these QPs.
====================

For dependencies this branch is based on mlx5-next from
git://git.kernel.org/pub/scm/linux/kernel/git/mellanox/linux

* branch 'mlx5_tir_icm':
  IB/mlx5: Expose TIR ICM address to user space
  net/mlx5: Introduce new TIR creation core API
  net/mlx5: Expose TIR ICM address in command outbox

Signed-off-by: Jason Gunthorpe &lt;jgg@mellanox.com&gt;
</content>
</entry>
<entry>
<title>IB/mlx5: Expose TIR ICM address to user space</title>
<updated>2019-04-25T13:03:19Z</updated>
<author>
<name>Ariel Levkovich</name>
<email>lariel@mellanox.com</email>
</author>
<published>2019-03-31T16:44:50Z</published>
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<id>urn:sha1:1f1d6abbf0bebe4b1fc33b80730a1b4bfbc8f7bb</id>
<content type='text'>
This patch exposes the TIR ICM address of raw packet and RSS
QPs to user space.

In order to pass the new field, the patch extends the mlx5
specific QP creation response structure and fills it with
the icm address returned by the FW command, if available.

Signed-off-by: Ariel Levkovich &lt;lariel@mellanox.com&gt;
Signed-off-by: Leon Romanovsky &lt;leonro@mellanox.com&gt;
Signed-off-by: Jason Gunthorpe &lt;jgg@mellanox.com&gt;
</content>
</entry>
<entry>
<title>IB/mlx5: Fix scatter to CQE in DCT QP creation</title>
<updated>2019-04-18T06:13:41Z</updated>
<author>
<name>Guy Levi</name>
<email>guyle@mellanox.com</email>
</author>
<published>2019-04-10T07:59:45Z</published>
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<id>urn:sha1:7249c8ea227a582c14f63e9e8853eb7369122f10</id>
<content type='text'>
When scatter to CQE is enabled on a DCT QP it corrupts the mailbox command
since it tried to treat it as as QP create mailbox command instead of a
DCT create command.

The corrupted mailbox command causes userspace to malfunction as the
device doesn't create the QP as expected.

A new mlx5 capability is exposed to user-space which ensures that it will
not enable the feature on DCT without this fix in the kernel.

Fixes: 5d6ff1babe78 ("IB/mlx5: Support scatter to CQE for DC transport type")
Signed-off-by: Guy Levi &lt;guyle@mellanox.com&gt;
Signed-off-by: Leon Romanovsky &lt;leonro@mellanox.com&gt;
Signed-off-by: Jason Gunthorpe &lt;jgg@mellanox.com&gt;
</content>
</entry>
<entry>
<title>IB/mlx5: Report packet based credit mode device capability</title>
<updated>2018-12-07T20:22:09Z</updated>
<author>
<name>Danit Goldberg</name>
<email>danitg@mellanox.com</email>
</author>
<published>2018-11-30T11:22:06Z</published>
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<id>urn:sha1:7e11b911b520de6a3189fafa94740f5fde2a2c98</id>
<content type='text'>
Report packet based credit mode capability via the mlx5 DV interface.

Signed-off-by: Danit Goldberg &lt;danitg@mellanox.com&gt;
Reviewed-by: Majd Dibbiny &lt;majd@mellanox.com&gt;
Signed-off-by: Leon Romanovsky &lt;leonro@mellanox.com&gt;
Signed-off-by: Jason Gunthorpe &lt;jgg@mellanox.com&gt;
</content>
</entry>
<entry>
<title>IB/mlx5: Add packet based credit mode support</title>
<updated>2018-12-07T20:22:09Z</updated>
<author>
<name>Danit Goldberg</name>
<email>danitg@mellanox.com</email>
</author>
<published>2018-11-30T11:22:05Z</published>
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<id>urn:sha1:569c665150156e44ecbd92af47a6d3fd4e2e4690</id>
<content type='text'>
The device can support two credit modes, message based (default) and
packet based. In order to enable packet based mode, the QP should be
created with special flag that indicates this.

This patch adds support for the new DV QP creation flag that can be used
for RC QPs in order to change the credit mode.

Signed-off-by: Danit Goldberg &lt;danitg@mellanox.com&gt;
Reviewed-by: Majd Dibbiny &lt;majd@mellanox.com&gt;
Signed-off-by: Leon Romanovsky &lt;leonro@mellanox.com&gt;
Signed-off-by: Jason Gunthorpe &lt;jgg@mellanox.com&gt;
</content>
</entry>
<entry>
<title>IB/mlx5: Allow scatter to CQE without global signaled WRs</title>
<updated>2018-10-17T15:25:41Z</updated>
<author>
<name>Yonatan Cohen</name>
<email>yonatanc@mellanox.com</email>
</author>
<published>2018-10-09T09:05:15Z</published>
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<id>urn:sha1:6f4bc0ea682b59d7013cbc5ced2d4dd73067a33f</id>
<content type='text'>
Requester scatter to CQE is restricted to QPs configured to signal
all WRs.

This patch adds ability to enable scatter to cqe (force enable)
in the requester without sig_all, for users who do not want all WRs
signaled but rather just the ones whose data found in the CQE.

Signed-off-by: Yonatan Cohen &lt;yonatanc@mellanox.com&gt;
Reviewed-by: Guy Levi &lt;guyle@mellanox.com&gt;
Signed-off-by: Leon Romanovsky &lt;leonro@mellanox.com&gt;
Signed-off-by: Doug Ledford &lt;dledford@redhat.com&gt;
</content>
</entry>
<entry>
<title>IB/mlx5: Expose RAW QP device handles to user space</title>
<updated>2018-09-27T19:01:33Z</updated>
<author>
<name>Yishai Hadas</name>
<email>yishaih@mellanox.com</email>
</author>
<published>2018-09-20T18:45:18Z</published>
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<id>urn:sha1:7f72052cb48efb5637ed99d2f45cb33a0bf60719</id>
<content type='text'>
Expose RAW QP device handles to user space by extending the UHW part of
mlx5_ib_create_qp_resp.

This data is returned only when DEVX context is used where it may be
applicable.

Signed-off-by: Yishai Hadas &lt;yishaih@mellanox.com&gt;
Signed-off-by: Leon Romanovsky &lt;leonro@mellanox.com&gt;
Signed-off-by: Jason Gunthorpe &lt;jgg@mellanox.com&gt;
</content>
</entry>
<entry>
<title>RDMA/mlx5: Allow creating RAW ethernet QP with loopback support</title>
<updated>2018-09-22T00:20:59Z</updated>
<author>
<name>Mark Bloch</name>
<email>markb@mellanox.com</email>
</author>
<published>2018-09-17T10:30:48Z</published>
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<id>urn:sha1:175edba85634a8be0ddab5ee96d0b23d9f17627e</id>
<content type='text'>
Expose two new flags:
MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC
MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC

Those flags can be used at creation time in order to allow a QP
to be able to receive loopback traffic (unicast and multicast).
We store the state in the QP to be used on the destroy path
to indicate with which flags the QP was created with.

Signed-off-by: Mark Bloch &lt;markb@mellanox.com&gt;
Reviewed-by: Yishai Hadas &lt;yishaih@mellanox.com&gt;
Signed-off-by: Leon Romanovsky &lt;leonro@mellanox.com&gt;
Signed-off-by: Doug Ledford &lt;dledford@redhat.com&gt;
</content>
</entry>
<entry>
<title>Merge branch 'mlx5-dump-fill-mkey' into rdma.git for-next</title>
<updated>2018-07-04T19:23:46Z</updated>
<author>
<name>Jason Gunthorpe</name>
<email>jgg@mellanox.com</email>
</author>
<published>2018-07-04T19:19:46Z</published>
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<id>urn:sha1:8193abb6a8171c775503acd041eb957cc7e9e7f4</id>
<content type='text'>
For dependencies, branch based on 'mellanox/mlx5-next' of
git://git.kernel.org/pub/scm/linux/kernel/git/mellanox/linux.git

Pull Dump and fill MKEY from Leon Romanovsky:

====================
MLX5 IB HCA offers the memory key, dump_fill_mkey to increase performance,
when used in a send or receive operations.

It is used to force local HCA operations to skip the PCI bus access, while
keeping track of the processed length in the ibv_sge handling.

In this three patch series, we expose various bits in our HW spec
file (mlx5_ifc.h), move unneeded for mlx5_core FW command and export such
memory key to user space thought our mlx5-abi header file.
====================

Botched auto-merge in mlx5_ib_alloc_ucontext() resolved by hand.

* branch 'mlx5-dump-fill-mkey':
  IB/mlx5: Expose dump and fill memory key
  net/mlx5: Add hardware definitions for dump_fill_mkey
  net/mlx5: Limit scope of dump_fill_mkey function
  net/mlx5: Rate limit errors in command interface

Signed-off-by: Jason Gunthorpe &lt;jgg@mellanox.com&gt;
</content>
</entry>
<entry>
<title>IB/mlx5: Expose dump and fill memory key</title>
<updated>2018-07-04T19:16:04Z</updated>
<author>
<name>Yonatan Cohen</name>
<email>yonatanc@mellanox.com</email>
</author>
<published>2018-06-19T05:47:24Z</published>
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<id>urn:sha1:25bb36e75d7d62dc14ae2306dca38d672e0c3fa0</id>
<content type='text'>
MLX5 IB HCA offers the memory key, dump_fill_mkey to boost
performance, when used in a send or receive operations.

It is used to force local HCA operations to skip the PCI bus access,
while keeping track of the processed length in the ibv_sge handling.

Meaning, instead of a PCI write access the HCA leaves the target
memory untouched, and skips filling that packet section. Similar
behavior is done upon send, the HCA skips data in memory relevant
to this key and saves PCI bus access.

This functionality saves PCI read/write operations.

Signed-off-by: Yonatan Cohen &lt;yonatanc@mellanox.com&gt;
Reviewed-by: Yishai Hadas &lt;yishaih@mellanox.com&gt;
Reviewed-by: Guy Levi &lt;guyle@mellanox.com&gt;
Signed-off-by: Leon Romanovsky &lt;leonro@mellanox.com&gt;
Signed-off-by: Jason Gunthorpe &lt;jgg@mellanox.com&gt;
</content>
</entry>
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