<feed xmlns='http://www.w3.org/2005/Atom'>
<title>kernel/include/uapi/rdma/hns-abi.h, branch linux-6.16.y</title>
<subtitle>Hosts the 0x221E linux distro kernel.</subtitle>
<id>https://universe.0xinfinity.dev/distro/kernel/atom?h=linux-6.16.y</id>
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<updated>2024-04-09T07:27:41Z</updated>
<entry>
<title>RDMA/hns: Support DSCP</title>
<updated>2024-04-09T07:27:41Z</updated>
<author>
<name>Junxian Huang</name>
<email>huangjunxian6@hisilicon.com</email>
</author>
<published>2024-03-15T09:35:51Z</published>
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<id>urn:sha1:ee20cc17e9d8fd85225e18351637460f3482be2f</id>
<content type='text'>
Add support for DSCP configuration. For DSCP, get dscp-prio mapping
via hns3 nic driver api .get_dscp_prio() and fill the SL (in WQE for
UD or in QPC for RC) with the priority value. The prio-tc mapping is
configured to HW by hns3 nic driver. HW will select a corresponding
TC according to SL and the prio-tc mapping.

Signed-off-by: Junxian Huang &lt;huangjunxian6@hisilicon.com&gt;
Link: https://lore.kernel.org/r/20240315093551.1650088-1-huangjunxian6@hisilicon.com
Signed-off-by: Leon Romanovsky &lt;leon@kernel.org&gt;
</content>
</entry>
<entry>
<title>RDMA/hns: Support userspace configuring congestion control algorithm with QP granularity</title>
<updated>2024-03-03T13:01:33Z</updated>
<author>
<name>Junxian Huang</name>
<email>huangjunxian6@hisilicon.com</email>
</author>
<published>2024-03-01T10:48:45Z</published>
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<id>urn:sha1:6ec429d5887a41b2dc8d92e391552f5604085cc2</id>
<content type='text'>
Currently, congestion control algorithm is statically configured in
FW, and all QPs use the same algorithm(except UD which has a fixed
configuration of DCQCN). This is not flexible enough.

Support userspace configuring congestion control algorithm with QP
granularity while creating QPs. If the algorithm is not specified in
userspace, use the default one.

Signed-off-by: Junxian Huang &lt;huangjunxian6@hisilicon.com&gt;
Link: https://lore.kernel.org/r/20240301104845.1141083-1-huangjunxian6@hisilicon.com
Signed-off-by: Leon Romanovsky &lt;leon@kernel.org&gt;
</content>
</entry>
<entry>
<title>RDMA/hns: Response dmac to userspace</title>
<updated>2023-12-07T13:09:16Z</updated>
<author>
<name>Junxian Huang</name>
<email>huangjunxian6@hisilicon.com</email>
</author>
<published>2023-12-07T11:42:28Z</published>
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<id>urn:sha1:d3f4020a213e1cb125eed2363fca372a23f7de7a</id>
<content type='text'>
While creating AH, dmac is already resolved in kernel. Response dmac
to userspace so that userspace doesn't need to resolve dmac repeatedly.

Signed-off-by: Junxian Huang &lt;huangjunxian6@hisilicon.com&gt;
Link: https://lore.kernel.org/r/20231207114231.2872104-3-huangjunxian6@hisilicon.com
Signed-off-by: Leon Romanovsky &lt;leon@kernel.org&gt;
</content>
</entry>
<entry>
<title>RDMA/hns: Support SRQ record doorbell</title>
<updated>2023-10-02T08:47:08Z</updated>
<author>
<name>Yangyang Li</name>
<email>liyangyang20@huawei.com</email>
</author>
<published>2023-09-26T13:00:26Z</published>
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<id>urn:sha1:c9813b0b9992eab01a47ad8d10f0add13f898692</id>
<content type='text'>
Compared with normal doorbell, using record doorbell can shorten the
process of ringing the doorbell and reduce the latency.

Add a flag HNS_ROCE_CAP_FLAG_SRQ_RECORD_DB to allow FW to
enable/disable SRQ record doorbell.

If the flag above is set, allocate the dma buffer for SRQ record
doorbell and write the buffer address into SRQC during SRQ creation.

For userspace SRQ, add a flag HNS_ROCE_RSP_SRQ_CAP_RECORD_DB to notify
userspace whether the SRQ record doorbell is enabled.

Signed-off-by: Yangyang Li &lt;liyangyang20@huawei.com&gt;
Signed-off-by: Junxian Huang &lt;huangjunxian6@hisilicon.com&gt;
Link: https://lore.kernel.org/r/20230926130026.583088-1-huangjunxian6@hisilicon.com
Signed-off-by: Leon Romanovsky &lt;leon@kernel.org&gt;
</content>
</entry>
<entry>
<title>RDMA/hns: Support cqe inline in user space</title>
<updated>2023-01-09T14:45:28Z</updated>
<author>
<name>Luoyouming</name>
<email>luoyouming@huawei.com</email>
</author>
<published>2022-12-24T10:22:01Z</published>
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<id>urn:sha1:1d91855304c2046115ee10be2c93161d93d5d40d</id>
<content type='text'>
Enable the CQEIE field and configure the CQEIS field of QPC.  And add
compatibility handling.

Link: https://lore.kernel.org/r/20221224102201.3114536-4-xuhaoyue1@hisilicon.com
Signed-off-by: Luoyouming &lt;luoyouming@huawei.com&gt;
Signed-off-by: Haoyue Xu &lt;xuhaoyue1@hisilicon.com&gt;
Signed-off-by: Jason Gunthorpe &lt;jgg@nvidia.com&gt;
</content>
</entry>
<entry>
<title>RDMA/hns: Add compatibility handling for only support userspace rq inline</title>
<updated>2023-01-09T14:45:28Z</updated>
<author>
<name>Luoyouming</name>
<email>luoyouming@huawei.com</email>
</author>
<published>2022-12-24T10:22:00Z</published>
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<id>urn:sha1:2bb185c68bf4c147f43d932e8a34fa150d148940</id>
<content type='text'>
The rq inline makes some changes as follows, Firstly, it is only used in
user space. Secondly, it should notify hardware in QP RTR status. Thirdly,
Add compatibility processing between different user space and kernel
space.

Link: https://lore.kernel.org/r/20221224102201.3114536-3-xuhaoyue1@hisilicon.com
Signed-off-by: Luoyouming &lt;luoyouming@huawei.com&gt;
Signed-off-by: Haoyue Xu &lt;xuhaoyue1@hisilicon.com&gt;
Signed-off-by: Jason Gunthorpe &lt;jgg@nvidia.com&gt;
</content>
</entry>
<entry>
<title>RDMA/hns: Fix incorrect sge nums calculation</title>
<updated>2022-11-19T00:19:49Z</updated>
<author>
<name>Luoyouming</name>
<email>luoyouming@huawei.com</email>
</author>
<published>2022-11-08T13:38:47Z</published>
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<id>urn:sha1:0c5e259b06a8efc69f929ad777ea49281bb58e37</id>
<content type='text'>
The user usually configures the number of sge through the max_send_sge
parameter when creating qp, and configures the maximum size of inline data
that can be sent through max_inline_data. Inline uses sge to fill data to
send. Expect the following:

1) When the sge space cannot hold inline data, the sge space needs to be
   expanded to accommodate all inline data

2) When the sge space is enough to accommodate inline data, the upper
   limit of inline data can be increased so that users can send larger
   inline data

Currently case one is not implemented. When the inline data is larger than
the sge space, an error of insufficient sge space occurs.  This part of
the code needs to be reimplemented according to the expected rules. The
calculation method of sge num is modified to take the maximum value of
max_send_sge and the sge for max_inline_data to solve this problem.

Fixes: 05201e01be93 ("RDMA/hns: Refactor process of setting extended sge")
Fixes: 30b707886aeb ("RDMA/hns: Support inline data in extented sge space for RC")
Link: https://lore.kernel.org/r/20221108133847.2304539-3-xuhaoyue1@hisilicon.com
Signed-off-by: Luoyouming &lt;luoyouming@huawei.com&gt;
Signed-off-by: Haoyue Xu &lt;xuhaoyue1@hisilicon.com&gt;
Signed-off-by: Jason Gunthorpe &lt;jgg@nvidia.com&gt;
</content>
</entry>
<entry>
<title>RDMA/hns: Support direct wqe of userspace</title>
<updated>2021-12-14T23:59:07Z</updated>
<author>
<name>Yixing Liu</name>
<email>liuyixing1@huawei.com</email>
</author>
<published>2021-12-07T12:49:01Z</published>
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<id>urn:sha1:0045e0d3f42ed7d05434bb5bc16acfc793ea4891</id>
<content type='text'>
The current write wqe mechanism is to write to DDR first, and then notify
the hardware through doorbell to read the data. Direct wqe is a mechanism
to fill wqe directly into the hardware. In the case of light load, the wqe
will be filled into pcie bar space of the hardware, this will reduce one
memory access operation and therefore reduce the latency. SIMD
instructions allows cpu to write the 512 bits at one time to device
memory, thus it can be used for posting direct wqe.

Add direct wqe enable switch and address mapping.

Link: https://lore.kernel.org/r/20211207124901.42123-2-liangwenpeng@huawei.com
Signed-off-by: Yixing Liu &lt;liuyixing1@huawei.com&gt;
Signed-off-by: Wenpeng Liang &lt;liangwenpeng@huawei.com&gt;
Signed-off-by: Jason Gunthorpe &lt;jgg@nvidia.com&gt;
</content>
</entry>
<entry>
<title>RDMA/hns: Add support for XRC on HIP09</title>
<updated>2021-03-11T23:51:27Z</updated>
<author>
<name>Wenpeng Liang</name>
<email>liangwenpeng@huawei.com</email>
</author>
<published>2021-03-04T02:55:58Z</published>
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<id>urn:sha1:32548870d438aba3c4a13f07efb73a8b86de507d</id>
<content type='text'>
The HIP09 supports XRC transport service, it greatly saves the number of
QPs required to connect all processes in a large cluster.

Link: https://lore.kernel.org/r/1614826558-35423-1-git-send-email-liweihang@huawei.com
Signed-off-by: Wenpeng Liang &lt;liangwenpeng@huawei.com&gt;
Signed-off-by: Weihang Li &lt;liweihang@huawei.com&gt;
Signed-off-by: Jason Gunthorpe &lt;jgg@nvidia.com&gt;
</content>
</entry>
<entry>
<title>RDMA/hns: Move capability flags of QP and CQ to hns-abi.h</title>
<updated>2020-12-07T19:48:51Z</updated>
<author>
<name>Weihang Li</name>
<email>liweihang@huawei.com</email>
</author>
<published>2020-12-02T01:29:20Z</published>
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<id>urn:sha1:53ef4999f07d9c75cdc8effb0cc8c581dc39b1a1</id>
<content type='text'>
These flags will be returned to the userspace through ABI, so they should
be defined in hns-abi.h. Furthermore, there is no need to include
hns-abi.h in every source files, it just needs to be included in the
common header file.

Link: https://lore.kernel.org/r/1606872560-17823-1-git-send-email-liweihang@huawei.com
Reported-by: kernel test robot &lt;lkp@intel.com&gt;
Signed-off-by: Weihang Li &lt;liweihang@huawei.com&gt;
Signed-off-by: Jason Gunthorpe &lt;jgg@nvidia.com&gt;
</content>
</entry>
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