<feed xmlns='http://www.w3.org/2005/Atom'>
<title>kernel/include/uapi/linux/pci_regs.h, branch linux-6.11.y</title>
<subtitle>Hosts the 0x221E linux distro kernel.</subtitle>
<id>https://universe.0xinfinity.dev/distro/kernel/atom?h=linux-6.11.y</id>
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<updated>2024-05-16T23:14:09Z</updated>
<entry>
<title>Merge branch 'pci/doe'</title>
<updated>2024-05-16T23:14:09Z</updated>
<author>
<name>Bjorn Helgaas</name>
<email>bhelgaas@google.com</email>
</author>
<published>2024-05-16T23:14:09Z</published>
<link rel='alternate' type='text/html' href='https://universe.0xinfinity.dev/distro/kernel/commit/?id=d539117564bc5e504731db2f057075a323e11637'/>
<id>urn:sha1:d539117564bc5e504731db2f057075a323e11637</id>
<content type='text'>
- Add support for DOE Discovery version 2 (Alexey Kardashevskiy)

* pci/doe:
  PCI/DOE: Support discovery version 2
</content>
</entry>
<entry>
<title>PCI/CXL: Fail bus reset if upstream CXL Port has SBR masked</title>
<updated>2024-05-08T18:25:36Z</updated>
<author>
<name>Dave Jiang</name>
<email>dave.jiang@intel.com</email>
</author>
<published>2024-05-02T16:57:32Z</published>
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<id>urn:sha1:b1956e2d0713e210a56ae65ad3488ae36f833e76</id>
<content type='text'>
Per CXL spec r3.1, sec 8.1.5.2, the Secondary Bus Reset (SBR) bit in the
Bridge Control register of a CXL port has no effect unless the "Unmask SBR"
bit is set.

Return -ENOTTY if we attempt a bus reset on a device below a CXL Port where
"Unmask SBR" is 0.  Otherwise, the bus reset would appear to have succeeded
even though setting the bridge SBR bit had no effect.

Link: https://lore.kernel.org/linux-cxl/20240220203956.GA1502351@bhelgaas/
Link: https://lore.kernel.org/r/20240502165851.1948523-4-dave.jiang@intel.com
Signed-off-by: Dave Jiang &lt;dave.jiang@intel.com&gt;
[bhelgaas: simplify commit log and comments]
Signed-off-by: Bjorn Helgaas &lt;bhelgaas@google.com&gt;
Reviewed-by: Jonathan Cameron &lt;Jonathan.Cameron@huawei.com&gt;
Reviewed-by: Kuppuswamy Sathyanarayanan &lt;sathyanarayanan.kuppuswamy@linux.intel.com&gt;
Reviewed-by: Dan Williams &lt;dan.j.williams@intel.com&gt;
</content>
</entry>
<entry>
<title>PCI/DOE: Support discovery version 2</title>
<updated>2024-04-09T14:33:15Z</updated>
<author>
<name>Alexey Kardashevskiy</name>
<email>aik@amd.com</email>
</author>
<published>2024-03-07T02:20:06Z</published>
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<id>urn:sha1:eebab7e3eb4bb906a8ebc3b70d28059ff1d9271c</id>
<content type='text'>
PCIe r6.1, sec 6.30.1.1 defines a "DOE Discovery Version" field in
the DOE Discovery Request Data Object Contents (3rd DW) as:

15:8 DOE Discovery Version – must be 02h if the Capability Version in
the Data Object Exchange Extended Capability is 02h or greater.

Add support for the version on devices with the DOE v2 capability.

Link: https://lore.kernel.org/r/20240307022006.3657433-1-aik@amd.com
Signed-off-by: Alexey Kardashevskiy &lt;aik@amd.com&gt;
Signed-off-by: Bjorn Helgaas &lt;bhelgaas@google.com&gt;
Reviewed-by: Kuppuswamy Sathyanarayanan &lt;sathyanarayanan.kuppuswamy@linux.intel.com&gt;
</content>
</entry>
<entry>
<title>Merge branch 'pci/field-get'</title>
<updated>2023-10-28T18:31:05Z</updated>
<author>
<name>Bjorn Helgaas</name>
<email>bhelgaas@google.com</email>
</author>
<published>2023-10-28T18:31:05Z</published>
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<id>urn:sha1:5897c174028a6a05169b6ecdbcd20fe4d1a8bcda</id>
<content type='text'>
- Use FIELD_GET()/FIELD_PREP() when possible throughout drivers/pci/ (Ilpo
  Järvinen, Bjorn Helgaas)

- Rework DPC control programming for clarity (Ilpo Järvinen)

* pci/field-get:
  PCI/portdrv: Use FIELD_GET()
  PCI/VC: Use FIELD_GET()
  PCI/PTM: Use FIELD_GET()
  PCI/PME: Use FIELD_GET()
  PCI/ATS: Use FIELD_GET()
  PCI/ATS: Show PASID Capability register width in bitmasks
  PCI: Use FIELD_GET() in Sapphire RX 5600 XT Pulse quirk
  PCI: Use FIELD_GET()
  PCI/MSI: Use FIELD_GET/PREP()
  PCI/DPC: Use defines with DPC reason fields
  PCI/DPC: Use defined fields with DPC_CTL register
  PCI/DPC: Use FIELD_GET()
  PCI: hotplug: Use FIELD_GET/PREP()
  PCI: dwc: Use FIELD_GET/PREP()
  PCI: cadence: Use FIELD_GET()
  PCI: Use FIELD_GET() to extract Link Width
  PCI: mvebu: Use FIELD_PREP() with Link Width
  PCI: tegra194: Use FIELD_GET()/FIELD_PREP() with Link Width fields

# Conflicts:
#	drivers/pci/controller/dwc/pcie-tegra194.c
</content>
</entry>
<entry>
<title>Merge branch 'pci/enumeration'</title>
<updated>2023-10-28T18:30:58Z</updated>
<author>
<name>Bjorn Helgaas</name>
<email>bhelgaas@google.com</email>
</author>
<published>2023-10-28T18:30:58Z</published>
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<id>urn:sha1:553b84bf467746b95f893f1bb92b143674a1aaf0</id>
<content type='text'>
- Add and use pci_get_base_class() to search for all PCI_BASE_CLASS_DISPLAY
  devices (Sui Jingfeng)

- Fix a vmd check for multi-function devices (Ilpo Järvinen)

- Add PCI_HEADER_TYPE_MFD and use it to replace literals (Ilpo Järvinen)

- Use acpi_evaluate_dsm_typed() instead of open-coding it (Andy Shevchenko)

- Keep .remove() and .probe() callbacks (previously marked __init) in case
  they're used via sysfs (Uwe Kleine-König)

* pci/enumeration:
  PCI: keystone: Don't discard .probe() callback
  PCI: keystone: Don't discard .remove() callback
  PCI: kirin: Don't discard .remove() callback
  PCI: exynos: Don't discard .remove() callback
  PCI/ACPI: Use acpi_evaluate_dsm_typed()
  PCI: Use PCI_HEADER_TYPE_* instead of literals
  PCI: Add PCI_HEADER_TYPE_MFD definition
  PCI: vmd: Correct PCI Header Type Register's multi-function check
  drm/radeon: Use pci_get_base_class() to reduce duplicated code
  drm/amdgpu: Use pci_get_base_class() to reduce duplicated code
  drm/nouveau: Use pci_get_base_class() to reduce duplicated code
  ALSA: hda: Use pci_get_base_class() to reduce duplicated code
  PCI: Add pci_get_base_class() helper
</content>
</entry>
<entry>
<title>PCI/PME: Use FIELD_GET()</title>
<updated>2023-10-24T21:55:45Z</updated>
<author>
<name>Bjorn Helgaas</name>
<email>bhelgaas@google.com</email>
</author>
<published>2023-10-10T20:44:33Z</published>
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<id>urn:sha1:ec302b118a59785511d6f90592a8be097d67341c</id>
<content type='text'>
Use FIELD_GET() to remove dependences on the field position, i.e., the
shift value.  No functional change intended.

Link: https://lore.kernel.org/r/20231010204436.1000644-8-helgaas@kernel.org
Signed-off-by: Bjorn Helgaas &lt;bhelgaas@google.com&gt;
Reviewed-by: Ilpo Järvinen &lt;ilpo.jarvinen@linux.intel.com&gt;
Reviewed-by: Jonathan Cameron &lt;Jonathan.Cameron@huawei.com&gt;
Reviewed-by: Kuppuswamy Sathyanarayanan &lt;sathyanarayanan.kuppuswamy@linux.intel.com&gt;
</content>
</entry>
<entry>
<title>PCI/ATS: Use FIELD_GET()</title>
<updated>2023-10-24T21:55:45Z</updated>
<author>
<name>Bjorn Helgaas</name>
<email>bhelgaas@google.com</email>
</author>
<published>2023-10-10T20:44:31Z</published>
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<id>urn:sha1:e0701bd0e6669e4c4b0d11254f5948ebf8d0b732</id>
<content type='text'>
Use FIELD_GET() to remove dependences on the field position, i.e., the
shift value.  No functional change intended.

Link: https://lore.kernel.org/r/20231010204436.1000644-6-helgaas@kernel.org
Signed-off-by: Bjorn Helgaas &lt;bhelgaas@google.com&gt;
Reviewed-by: Jonathan Cameron &lt;Jonathan.Cameron@huawei.com&gt;
Reviewed-by: Ilpo Järvinen &lt;ilpo.jarvinen@linux.intel.com&gt;
Reviewed-by: Kuppuswamy Sathyanarayanan &lt;sathyanarayanan.kuppuswamy@linux.intel.com&gt;
</content>
</entry>
<entry>
<title>PCI/ATS: Show PASID Capability register width in bitmasks</title>
<updated>2023-10-24T21:55:45Z</updated>
<author>
<name>Bjorn Helgaas</name>
<email>bhelgaas@google.com</email>
</author>
<published>2023-10-10T20:44:30Z</published>
<link rel='alternate' type='text/html' href='https://universe.0xinfinity.dev/distro/kernel/commit/?id=d30fea25845ff65ea1fb255d7b615cd02b65095b'/>
<id>urn:sha1:d30fea25845ff65ea1fb255d7b615cd02b65095b</id>
<content type='text'>
The PASID Capability and Control registers are both 16 bits wide.  Use
16-bit wide constants in field names to match the register width.  No
functional change intended.

Link: https://lore.kernel.org/r/20231010204436.1000644-5-helgaas@kernel.org
Signed-off-by: Bjorn Helgaas &lt;bhelgaas@google.com&gt;
Reviewed-by: Ilpo Järvinen &lt;ilpo.jarvinen@linux.intel.com&gt;
Reviewed-by: Jonathan Cameron &lt;Jonathan.Cameron@huawei.com&gt;
Reviewed-by: Kuppuswamy Sathyanarayanan &lt;sathyanarayanan.kuppuswamy@linux.intel.com&gt;
</content>
</entry>
<entry>
<title>PCI/DPC: Use defines with DPC reason fields</title>
<updated>2023-10-24T15:54:04Z</updated>
<author>
<name>Ilpo Järvinen</name>
<email>ilpo.jarvinen@linux.intel.com</email>
</author>
<published>2023-10-18T11:32:53Z</published>
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<id>urn:sha1:74f0b5ffe172f913c56e4f5291678bad2a55b6b1</id>
<content type='text'>
Add new defines for DPC reason fields and use them instead of literals.

Link: https://lore.kernel.org/r/20231018113254.17616-7-ilpo.jarvinen@linux.intel.com
Signed-off-by: Ilpo Järvinen &lt;ilpo.jarvinen@linux.intel.com&gt;
[bhelgaas: shorten comments]
Signed-off-by: Bjorn Helgaas &lt;bhelgaas@google.com&gt;
</content>
</entry>
<entry>
<title>PCI/DPC: Use FIELD_GET()</title>
<updated>2023-10-24T15:54:04Z</updated>
<author>
<name>Bjorn Helgaas</name>
<email>bhelgaas@google.com</email>
</author>
<published>2023-10-18T11:32:51Z</published>
<link rel='alternate' type='text/html' href='https://universe.0xinfinity.dev/distro/kernel/commit/?id=9a9eec4765737b9b2a8d6ae03de6480a5f12dd5c'/>
<id>urn:sha1:9a9eec4765737b9b2a8d6ae03de6480a5f12dd5c</id>
<content type='text'>
Use FIELD_GET() to remove dependencies on the field position, i.e., the
shift value. No functional change intended.

Link: https://lore.kernel.org/r/20231018113254.17616-5-ilpo.jarvinen@linux.intel.com
Signed-off-by: Ilpo Järvinen &lt;ilpo.jarvinen@linux.intel.com&gt;
Signed-off-by: Bjorn Helgaas &lt;bhelgaas@google.com&gt;
</content>
</entry>
</feed>
