<feed xmlns='http://www.w3.org/2005/Atom'>
<title>kernel/include/uapi/linux/dpll.h, branch linux-6.17.y</title>
<subtitle>Hosts the 0x221E linux distro kernel.</subtitle>
<id>https://universe.0xinfinity.dev/distro/kernel/atom?h=linux-6.17.y</id>
<link rel='self' href='https://universe.0xinfinity.dev/distro/kernel/atom?h=linux-6.17.y'/>
<link rel='alternate' type='text/html' href='https://universe.0xinfinity.dev/distro/kernel/'/>
<updated>2025-06-27T23:38:02Z</updated>
<entry>
<title>dpll: add reference-sync netlink attribute</title>
<updated>2025-06-27T23:38:02Z</updated>
<author>
<name>Arkadiusz Kubalewski</name>
<email>arkadiusz.kubalewski@intel.com</email>
</author>
<published>2025-06-26T13:52:17Z</published>
<link rel='alternate' type='text/html' href='https://universe.0xinfinity.dev/distro/kernel/commit/?id=7f15ee35972dd3dee37704bfd0f136290f6d63d9'/>
<id>urn:sha1:7f15ee35972dd3dee37704bfd0f136290f6d63d9</id>
<content type='text'>
Add new netlink attribute to allow user space configuration of reference
sync pin pairs, where both pins are used to provide one clock signal
consisting of both: base frequency and sync signal.

Reviewed-by: Przemek Kitszel &lt;przemyslaw.kitszel@intel.com&gt;
Reviewed-by: Milena Olech &lt;milena.olech@intel.com&gt;
Reviewed-by: Jiri Pirko &lt;jiri@nvidia.com&gt;
Signed-off-by: Arkadiusz Kubalewski &lt;arkadiusz.kubalewski@intel.com&gt;
Link: https://patch.msgid.link/20250626135219.1769350-2-arkadiusz.kubalewski@intel.com
Signed-off-by: Jakub Kicinski &lt;kuba@kernel.org&gt;
</content>
</entry>
<entry>
<title>dpll: add phase-offset-monitor feature to netlink spec</title>
<updated>2025-06-14T01:21:57Z</updated>
<author>
<name>Arkadiusz Kubalewski</name>
<email>arkadiusz.kubalewski@intel.com</email>
</author>
<published>2025-06-12T15:28:33Z</published>
<link rel='alternate' type='text/html' href='https://universe.0xinfinity.dev/distro/kernel/commit/?id=c035e736038045b411cb368e63f07bc2f5dbc0e1'/>
<id>urn:sha1:c035e736038045b411cb368e63f07bc2f5dbc0e1</id>
<content type='text'>
Add enum dpll_feature_state for control over features.

Add dpll device level attribute:
DPLL_A_PHASE_OFFSET_MONITOR - to allow control over a phase offset monitor
feature. Attribute is present and shall return current state of a feature
(enum dpll_feature_state), if the device driver provides such capability,
otherwie attribute shall not be present.

Reviewed-by: Aleksandr Loktionov &lt;aleksandr.loktionov@intel.com&gt;
Reviewed-by: Milena Olech &lt;milena.olech@intel.com&gt;
Reviewed-by: Jiri Pirko &lt;jiri@nvidia.com&gt;
Signed-off-by: Arkadiusz Kubalewski &lt;arkadiusz.kubalewski@intel.com&gt;
Acked-by: Vadim Fedorenko &lt;vadim.fedorenko@linux.dev&gt;
Link: https://patch.msgid.link/20250612152835.1703397-2-arkadiusz.kubalewski@intel.com
Signed-off-by: Jakub Kicinski &lt;kuba@kernel.org&gt;
</content>
</entry>
<entry>
<title>tools: ynl-gen: de-kdocify enums with no doc for entries</title>
<updated>2024-11-05T02:11:47Z</updated>
<author>
<name>Jakub Kicinski</name>
<email>kuba@kernel.org</email>
</author>
<published>2024-11-03T16:53:14Z</published>
<link rel='alternate' type='text/html' href='https://universe.0xinfinity.dev/distro/kernel/commit/?id=690e50dd69ee48e43e0f7c42396487da1b81be14'/>
<id>urn:sha1:690e50dd69ee48e43e0f7c42396487da1b81be14</id>
<content type='text'>
Sometimes the names of the enum entries are self-explanatory
or come from standards. Forcing authors to write trivial kdoc
for each of such entries seems unreasonable, but kdoc would
complain about undocumented entries.

Detect enums which only have documentation for the entire
type and no documentation for entries. Render their doc
as a plain comment.

Link: https://patch.msgid.link/20241103165314.1631237-1-kuba@kernel.org
Signed-off-by: Jakub Kicinski &lt;kuba@kernel.org&gt;
</content>
</entry>
<entry>
<title>dpll: add clock quality level attribute and op</title>
<updated>2024-11-03T16:39:07Z</updated>
<author>
<name>Jiri Pirko</name>
<email>jiri@nvidia.com</email>
</author>
<published>2024-10-30T08:11:56Z</published>
<link rel='alternate' type='text/html' href='https://universe.0xinfinity.dev/distro/kernel/commit/?id=a1afb959add1fad43cb337448c244ed70bac3109'/>
<id>urn:sha1:a1afb959add1fad43cb337448c244ed70bac3109</id>
<content type='text'>
In order to allow driver expose quality level of the clock it is
running, introduce a new netlink attr with enum to carry it to the
userspace. Also, introduce an op the dpll netlink code calls into the
driver to obtain the value.

Signed-off-by: Jiri Pirko &lt;jiri@nvidia.com&gt;
Link: https://patch.msgid.link/20241030081157.966604-2-jiri@resnulli.us
Signed-off-by: Jakub Kicinski &lt;kuba@kernel.org&gt;
</content>
</entry>
<entry>
<title>dpll: add Embedded SYNC feature for a pin</title>
<updated>2024-08-27T02:21:14Z</updated>
<author>
<name>Arkadiusz Kubalewski</name>
<email>arkadiusz.kubalewski@intel.com</email>
</author>
<published>2024-08-22T22:25:12Z</published>
<link rel='alternate' type='text/html' href='https://universe.0xinfinity.dev/distro/kernel/commit/?id=cda1fba15cb2282b3c364805c9767698f11c3b0e'/>
<id>urn:sha1:cda1fba15cb2282b3c364805c9767698f11c3b0e</id>
<content type='text'>
Implement and document new pin attributes for providing Embedded SYNC
capabilities to the DPLL subsystem users through a netlink pin-get
do/dump messages. Allow the user to set Embedded SYNC frequency with
pin-set do netlink message.

Reviewed-by: Aleksandr Loktionov &lt;aleksandr.loktionov@intel.com&gt;
Signed-off-by: Arkadiusz Kubalewski &lt;arkadiusz.kubalewski@intel.com&gt;
Reviewed-by: Jiri Pirko &lt;jiri@nvidia.com&gt;
Link: https://patch.msgid.link/20240822222513.255179-2-arkadiusz.kubalewski@intel.com
Signed-off-by: Jakub Kicinski &lt;kuba@kernel.org&gt;
</content>
</entry>
<entry>
<title>dpll: extend uapi by lock status error attribute</title>
<updated>2024-02-01T14:39:44Z</updated>
<author>
<name>Jiri Pirko</name>
<email>jiri@nvidia.com</email>
</author>
<published>2024-01-30T12:08:29Z</published>
<link rel='alternate' type='text/html' href='https://universe.0xinfinity.dev/distro/kernel/commit/?id=cf4f0f1e1c465da7c1f6bc89c3ff50bf42f0ab02'/>
<id>urn:sha1:cf4f0f1e1c465da7c1f6bc89c3ff50bf42f0ab02</id>
<content type='text'>
If the dpll devices goes to state "unlocked" or "holdover", it may be
caused by an error. In that case, allow user to see what the error was.
Introduce a new attribute and values it can carry.

Signed-off-by: Jiri Pirko &lt;jiri@nvidia.com&gt;
Acked-by: Vadim Fedorenko &lt;vadim.fedorenko@linux.dev&gt;
Reviewed-by: Simon Horman &lt;horms@kernel.org&gt;
Signed-off-by: Paolo Abeni &lt;pabeni@redhat.com&gt;
</content>
</entry>
<entry>
<title>dpll: expose fractional frequency offset value to user</title>
<updated>2024-01-05T15:58:19Z</updated>
<author>
<name>Jiri Pirko</name>
<email>jiri@nvidia.com</email>
</author>
<published>2024-01-03T13:28:36Z</published>
<link rel='alternate' type='text/html' href='https://universe.0xinfinity.dev/distro/kernel/commit/?id=8a6286c1804e2c7144aef3154a0357c4b496e10b'/>
<id>urn:sha1:8a6286c1804e2c7144aef3154a0357c4b496e10b</id>
<content type='text'>
Add a new netlink attribute to expose fractional frequency offset value
for a pin. Add an op to get the value from the driver.

Signed-off-by: Jiri Pirko &lt;jiri@nvidia.com&gt;
Acked-by: Vadim Fedorenko &lt;vadim.fedorenko@linux.dev&gt;
Acked-by: Arkadiusz Kubalewski &lt;arkadiusz.kubalewski@intel.com&gt;
Link: https://lore.kernel.org/r/20240103132838.1501801-2-jiri@resnulli.us
Signed-off-by: Jakub Kicinski &lt;kuba@kernel.org&gt;
</content>
</entry>
<entry>
<title>dpll: spec: add support for pin-dpll signal phase offset/adjust</title>
<updated>2023-10-15T15:08:24Z</updated>
<author>
<name>Arkadiusz Kubalewski</name>
<email>arkadiusz.kubalewski@intel.com</email>
</author>
<published>2023-10-11T10:12:33Z</published>
<link rel='alternate' type='text/html' href='https://universe.0xinfinity.dev/distro/kernel/commit/?id=c3c6ab95c397134bf5948f18743b3ba8008e7c47'/>
<id>urn:sha1:c3c6ab95c397134bf5948f18743b3ba8008e7c47</id>
<content type='text'>
Add attributes for providing the user with:
- measurement of signals phase offset between pin and dpll
- ability to adjust the phase of pin signal

Signed-off-by: Arkadiusz Kubalewski &lt;arkadiusz.kubalewski@intel.com&gt;
Signed-off-by: David S. Miller &lt;davem@davemloft.net&gt;
</content>
</entry>
<entry>
<title>dpll: spec: Add Netlink spec in YAML</title>
<updated>2023-09-17T10:50:20Z</updated>
<author>
<name>Vadim Fedorenko</name>
<email>vadim.fedorenko@linux.dev</email>
</author>
<published>2023-09-13T20:49:36Z</published>
<link rel='alternate' type='text/html' href='https://universe.0xinfinity.dev/distro/kernel/commit/?id=3badff3a25d815e915d89565a0c82dec608a8d2b'/>
<id>urn:sha1:3badff3a25d815e915d89565a0c82dec608a8d2b</id>
<content type='text'>
Add a protocol spec for DPLL.
Add code generated from the spec.

Signed-off-by: Jakub Kicinski &lt;kuba@kernel.org&gt;
Signed-off-by: Michal Michalik &lt;michal.michalik@intel.com&gt;
Signed-off-by: Vadim Fedorenko &lt;vadim.fedorenko@linux.dev&gt;
Signed-off-by: Arkadiusz Kubalewski &lt;arkadiusz.kubalewski@intel.com&gt;
Signed-off-by: Jiri Pirko &lt;jiri@nvidia.com&gt;
Signed-off-by: David S. Miller &lt;davem@davemloft.net&gt;
</content>
</entry>
</feed>
