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<title>kernel/include/uapi/drm/i915_drm.h, branch linux-3.17.y</title>
<subtitle>Hosts the 0x221E linux distro kernel.</subtitle>
<id>https://universe.0xinfinity.dev/distro/kernel/atom?h=linux-3.17.y</id>
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<updated>2014-05-16T17:31:29Z</updated>
<entry>
<title>drm/i915: Introduce mapping of user pages into video memory (userptr) ioctl</title>
<updated>2014-05-16T17:31:29Z</updated>
<author>
<name>Chris Wilson</name>
<email>chris@chris-wilson.co.uk</email>
</author>
<published>2014-05-16T13:22:37Z</published>
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<id>urn:sha1:5cc9ed4b9a7ac579362ccebac67f7a4cdb36de06</id>
<content type='text'>
By exporting the ability to map user address and inserting PTEs
representing their backing pages into the GTT, we can exploit UMA in order
to utilize normal application data as a texture source or even as a
render target (depending upon the capabilities of the chipset). This has
a number of uses, with zero-copy downloads to the GPU and efficient
readback making the intermixed streaming of CPU and GPU operations
fairly efficient. This ability has many widespread implications from
faster rendering of client-side software rasterisers (chromium),
mitigation of stalls due to read back (firefox) and to faster pipelining
of texture data (such as pixel buffer objects in GL or data blobs in CL).

v2: Compile with CONFIG_MMU_NOTIFIER
v3: We can sleep while performing invalidate-range, which we can utilise
to drop our page references prior to the kernel manipulating the vma
(for either discard or cloning) and so protect normal users.
v4: Only run the invalidate notifier if the range intercepts the bo.
v5: Prevent userspace from attempting to GTT mmap non-page aligned buffers
v6: Recheck after reacquire mutex for lost mmu.
v7: Fix implicit padding of ioctl struct by rounding to next 64bit boundary.
v8: Fix rebasing error after forwarding porting the back port.
v9: Limit the userptr to page aligned entries. We now expect userspace
    to handle all the offset-in-page adjustments itself.
v10: Prevent vma from being copied across fork to avoid issues with cow.
v11: Drop vma behaviour changes -- locking is nigh on impossible.
     Use a worker to load user pages to avoid lock inversions.
v12: Use get_task_mm()/mmput() for correct refcounting of mm.
v13: Use a worker to release the mmu_notifier to avoid lock inversion
v14: Decouple mmu_notifier from struct_mutex using a custom mmu_notifer
     with its own locking and tree of objects for each mm/mmu_notifier.
v15: Prevent overlapping userptr objects, and invalidate all objects
     within the mmu_notifier range
v16: Fix a typo for iterating over multiple objects in the range and
     rearrange error path to destroy the mmu_notifier locklessly.
     Also close a race between invalidate_range and the get_pages_worker.
v17: Close a race between get_pages_worker/invalidate_range and fresh
     allocations of the same userptr range - and notice that
     struct_mutex was presumed to be held when during creation it wasn't.
v18: Sigh. Fix the refactor of st_set_pages() to allocate enough memory
     for the struct sg_table and to clear it before reporting an error.
v19: Always error out on read-only userptr requests as we don't have the
     hardware infrastructure to support them at the moment.
v20: Refuse to implement read-only support until we have the required
     infrastructure - but reserve the bit in flags for future use.
v21: use_mm() is not required for get_user_pages(). It is only meant to
     be used to fix up the kernel thread's current-&gt;mm for use with
     copy_user().
v22: Use sg_alloc_table_from_pages for that chunky feeling
v23: Export a function for sanity checking dma-buf rather than encode
     userptr details elsewhere, and clean up comments based on
     suggestions by Bradley.

Signed-off-by: Chris Wilson &lt;chris@chris-wilson.co.uk&gt;
Cc: Tvrtko Ursulin &lt;tvrtko.ursulin@linux.intel.com&gt;
Cc: "Gong, Zhipeng" &lt;zhipeng.gong@intel.com&gt;
Cc: Akash Goel &lt;akash.goel@intel.com&gt;
Cc: "Volkin, Bradley D" &lt;bradley.d.volkin@intel.com&gt;
Reviewed-by: Tvrtko Ursulin &lt;tvrtko.ursulin@linux.intel.com&gt;
Reviewed-by: Brad Volkin &lt;bradley.d.volkin@intel.com&gt;
[danvet: Frob ioctl allocation to pick the next one - will cause a bit
of fuss with create2 apparently, but such are the rules.]
[danvet2: oops, forgot to git add after manual patch application]
[danvet3: Appease sparse.]
Signed-off-by: Daniel Vetter &lt;daniel.vetter@ffwll.ch&gt;
</content>
</entry>
<entry>
<title>drm/i915: Add a CMD_PARSER_VERSION getparam</title>
<updated>2014-04-01T20:58:15Z</updated>
<author>
<name>Brad Volkin</name>
<email>bradley.d.volkin@intel.com</email>
</author>
<published>2014-02-18T18:15:56Z</published>
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<id>urn:sha1:d728c8ef8bea6e81f44933c0237531cda499577e</id>
<content type='text'>
So userspace can query the kernel for command parser support.

v2: Add i915_cmd_parser_get_version(), history log, and kerneldoc

OTC-Tracker: AXIA-4631
Change-Id: I58af650db9f6753c2dcac9c54ab432fd31db302f
Signed-off-by: Brad Volkin &lt;bradley.d.volkin@intel.com&gt;
Reviewed-by: Jani Nikula &lt;jani.nikula@intel.com&gt;
Signed-off-by: Daniel Vetter &lt;daniel.vetter@ffwll.ch&gt;
</content>
</entry>
<entry>
<title>drm/i915: Spelling s/auxilliary/auxiliary/</title>
<updated>2014-01-22T08:58:24Z</updated>
<author>
<name>Geert Uytterhoeven</name>
<email>geert+renesas@linux-m68k.org</email>
</author>
<published>2014-01-12T13:08:43Z</published>
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<id>urn:sha1:c3d19d3c3fb0085fbfb81f546abb8d50fdf58d17</id>
<content type='text'>
Signed-off-by: Geert Uytterhoeven &lt;geert+renesas@linux-m68k.org&gt;
Signed-off-by: Daniel Vetter &lt;daniel.vetter@ffwll.ch&gt;
</content>
</entry>
<entry>
<title>drm/i915: add i915_get_reset_stats_ioctl</title>
<updated>2013-11-12T13:15:48Z</updated>
<author>
<name>Mika Kuoppala</name>
<email>mika.kuoppala@linux.intel.com</email>
</author>
<published>2013-10-30T13:44:16Z</published>
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<id>urn:sha1:b6359918b885da7c7b58c050674278dbd06020ab</id>
<content type='text'>
This ioctl returns reset stats for specified context.

The struct returned contains context loss counters.

reset_count:    all resets across all contexts
batch_active:   active batches lost on resets
batch_pending:  pending batches lost on resets

v2: get rid of state tracking completely and deliver only counts. Idea
    from Chris Wilson.

v3: fix commit message

v4: default context handled inside i915_gem_context_get_hang_stats

v5: reset_count only for priviledged process

v6: ctx=0 needs CAP_SYS_ADMIN for batch_* counters (Chris Wilson)

v7: context hang stats never returns NULL

v8: rebased on top of reworked context hang stats
    DRM_RENDER_ALLOW for ioctl

v9: use DEFAULT_CONTEXT_ID. Improve comments for ioctl struct members

Signed-off-by: Mika Kuoppala &lt;mika.kuoppala@intel.com&gt;
Cc: Ian Romanick &lt;idr@freedesktop.org&gt;
Cc: Chris Wilson &lt;chris@chris-wilson.co.uk&gt;
Cc: Daniel Vetter &lt;daniel.vetter@ffwll.ch&gt;
Reviewed-by: Damien Lespiau &lt;damien.lespiau@intel.com&gt;
Reviewed-by: Ian Romanick &lt;ian.d.romanick@intel.com&gt;
Signed-off-by: Daniel Vetter &lt;daniel.vetter@ffwll.ch&gt;
</content>
</entry>
<entry>
<title>drm/i915: Add second slice l3 remapping</title>
<updated>2013-09-19T18:37:04Z</updated>
<author>
<name>Ben Widawsky</name>
<email>benjamin.widawsky@intel.com</email>
</author>
<published>2013-09-19T18:13:41Z</published>
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<id>urn:sha1:35a85ac60618521d41cfdb14f3fbfc8ad7329e9e</id>
<content type='text'>
Certain HSW SKUs have a second bank of L3. This L3 remapping has a
separate register set, and interrupt from the first "slice". A slice is
simply a term to define some subset of the GPU's l3 cache. This patch
implements both the interrupt handler, and ability to communicate with
userspace about this second slice.

v2:  Remove redundant check about non-existent slice.
Change warning about interrupts of unknown slices to WARN_ON_ONCE
Handle the case where we get 2 slice interrupts concurrently, and switch
the tracking of interrupts to be non-destructive (all Ville)
Don't enable/mask the second slice parity interrupt for ivb/vlv (even
though all docs I can find claim it's rsvd) (Ville + Bryan)
Keep BYT excluded from L3 parity

v3: Fix the slice = ffs to be decremented by one (found by Ville). When
I initially did my testing on the series, I was using 1-based slice
counting, so this code was correct. Not sure why my simpler tests that
I've been running since then didn't pick it up sooner.

Reviewed-by: Ville Syrjälä &lt;ville.syrjala@linux.intel.com&gt;
Signed-off-by: Ben Widawsky &lt;ben@bwidawsk.net&gt;
Signed-off-by: Daniel Vetter &lt;daniel.vetter@ffwll.ch&gt;
</content>
</entry>
<entry>
<title>drm/i915: Use Write-Through cacheing for the display plane on Iris</title>
<updated>2013-08-22T11:31:38Z</updated>
<author>
<name>Chris Wilson</name>
<email>chris@chris-wilson.co.uk</email>
</author>
<published>2013-08-08T13:41:10Z</published>
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<id>urn:sha1:651d794fae9b79237aae1c97f8a9d9f3817bd31d</id>
<content type='text'>
Haswell GT3e has the unique feature of supporting Write-Through cacheing
of objects within the eLLC/LLC. The purpose of this is to enable the display
plane to remain coherent whilst objects lie resident in the eLLC/LLC - so
that we, in theory, get the best of both worlds, perfect display and fast
access.

However, we still need to be careful as the CPU does not see the WT when
accessing the cache. In particular, this means that we need to flush the
cache lines after writing to an object through the CPU, and on
transitioning from a cached state to WT.

v2: Actually do the clflush on transition to WT, nagging by Ville.
v3: Flush the CPU cache after writes into WT objects.
v4: Rease onto LLC updates and report WT as "uncached" for
get_cache_level_ioctl to remain symmetric with set_cache_level_ioctl.

Signed-off-by: Chris Wilson &lt;chris@chris-wilson.co.uk&gt;
Cc: Ville Syrjälä &lt;ville.syrjala@linux.intel.com&gt;
Cc: Kenneth Graunke &lt;kenneth@whitecape.org&gt;
Reviewed-by: Ville Syrjälä &lt;ville.syrjala@linux.intel.com&gt;
Signed-off-by: Daniel Vetter &lt;daniel.vetter@ffwll.ch&gt;
</content>
</entry>
<entry>
<title>drm/i915: reserve I915_CACHING_DISPLAY and document cache modes</title>
<updated>2013-08-22T11:31:34Z</updated>
<author>
<name>Daniel Vetter</name>
<email>daniel.vetter@ffwll.ch</email>
</author>
<published>2013-08-10T12:51:11Z</published>
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<id>urn:sha1:35c7ab421a13f8327e3fd627c6ebafb1c13b2e55</id>
<content type='text'>
Resolve the catch-22 of igt needing a stable number and patches first
needing testcases by reserving the interface number up-front.

v2: Improve the spelling a bit.

v3: More spelling fail spotted by Chris.

Requested-by: Chris Wilson &lt;chris@chris-wilson.co.uk&gt;
Cc: Chris Wilson &lt;chris@chris-wilson.co.uk&gt;
Cc: Ville Syrjälä &lt;ville.syrjala@linux.intel.com&gt;
Reviewed-by: Chris Wilson &lt;chris@chris-wilson.co.uk&gt;
Signed-off-by: Daniel Vetter &lt;daniel.vetter@ffwll.ch&gt;
</content>
</entry>
<entry>
<title>drm/i915: Make i915 events part of uapi</title>
<updated>2013-07-19T16:26:57Z</updated>
<author>
<name>Ben Widawsky</name>
<email>ben@bwidawsk.net</email>
</author>
<published>2013-07-19T16:16:42Z</published>
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<id>urn:sha1:cce723ed091ac304d48386bcc3524994c345123e</id>
<content type='text'>
Make the uevent strings part of the user API for people who wish to
write their own listeners.

v2: Make a space in the string concatenation. (Chad)
Use the "UEVENT" suffix intead of "EVENT" (Chad)
Make kernel-doc parseable Docbook comments (Daniel)

v3: Undid reset change introduced in last submission (Daniel)
Fixed up comments to address removal changes.

Thanks to Daniel Vetter for a majority of the parity error comments.

CC: Chad Versace &lt;chad.versace@linux.intel.com&gt;
Signed-off-by: Ben Widawsky &lt;ben@bwidawsk.net&gt;
Signed-off-by: Daniel Vetter &lt;daniel.vetter@ffwll.ch&gt;
</content>
</entry>
<entry>
<title>drm/i915: add I915_PARAM_HAS_VEBOX to i915_getparam</title>
<updated>2013-05-31T18:54:22Z</updated>
<author>
<name>Xiang, Haihao</name>
<email>haihao.xiang@intel.com</email>
</author>
<published>2013-05-29T02:22:34Z</published>
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<id>urn:sha1:a1f2cc73c762868435ae6ec9126bb2240337c61c</id>
<content type='text'>
This will let userland only try to use the new ring
when the appropriate kernel is present

Signed-off-by: Xiang, Haihao &lt;haihao.xiang@intel.com&gt;
Reviewed-by: Damien Lespiau &lt;damien.lespiau@intel.com&gt;
Signed-off-by: Ben Widawsky &lt;ben@bwidawsk.net&gt;
Signed-off-by: Daniel Vetter &lt;daniel.vetter@ffwll.ch&gt;
</content>
</entry>
<entry>
<title>drm/i915: add I915_EXEC_VEBOX to i915_gem_do_execbuffer()</title>
<updated>2013-05-31T18:54:21Z</updated>
<author>
<name>Xiang, Haihao</name>
<email>haihao.xiang@intel.com</email>
</author>
<published>2013-05-29T02:22:33Z</published>
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<id>urn:sha1:82f91b6e93e2138c7e02b5a866f63d04cf040c86</id>
<content type='text'>
A user can run batchbuffer via VEBOX ring.

Signed-off-by: Xiang, Haihao &lt;haihao.xiang@intel.com&gt;
Reviewed-by: Damien Lespiau &lt;damien.lespiau@intel.com&gt;
Signed-off-by: Ben Widawsky &lt;ben@bwidawsk.net&gt;
Signed-off-by: Daniel Vetter &lt;daniel.vetter@ffwll.ch&gt;
</content>
</entry>
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