<feed xmlns='http://www.w3.org/2005/Atom'>
<title>kernel/include/soc/tegra/fuse.h, branch linux-4.15.y</title>
<subtitle>Hosts the 0x221E linux distro kernel.</subtitle>
<id>https://universe.0xinfinity.dev/distro/kernel/atom?h=linux-4.15.y</id>
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<updated>2017-08-17T14:43:13Z</updated>
<entry>
<title>soc/tegra: Register SoC device</title>
<updated>2017-08-17T14:43:13Z</updated>
<author>
<name>Thierry Reding</name>
<email>treding@nvidia.com</email>
</author>
<published>2017-08-17T14:42:17Z</published>
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<id>urn:sha1:27a0342ac162bf2ba30c288cfb7b72eabed38d8b</id>
<content type='text'>
Move this code from arch/arm/mach-tegra and make it common among 32-bit
and 64-bit Tegra SoCs. This is slightly complicated by the fact that on
32-bit Tegra, the SoC device is used as the parent for all devices that
are instantiated from device tree.

Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>phy: tegra: Add Tegra210 support</title>
<updated>2016-04-29T14:44:48Z</updated>
<author>
<name>Thierry Reding</name>
<email>treding@nvidia.com</email>
</author>
<published>2015-11-11T17:25:02Z</published>
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<id>urn:sha1:87d66f280672800c9c2ad1ce3b7a993ce1e04769</id>
<content type='text'>
Add support for the XUSB pad controller found on Tegra210 SoCs. The
hardware is roughly the same, but some of the registers have been moved
around and the number and type of supported pads has changed.

Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>soc/tegra: fuse: Rename core_* to soc_*</title>
<updated>2015-07-16T08:38:29Z</updated>
<author>
<name>Thierry Reding</name>
<email>treding@nvidia.com</email>
</author>
<published>2015-03-23T13:44:08Z</published>
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<id>urn:sha1:03b3f4c8b76180ba5bd800c57a7efdb142c2341d</id>
<content type='text'>
There's a mixture of core_* and soc_* prefixes for variables storing
information related to the VDD_CORE rail. Choose one (soc_*) and use it
more consistently.

Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>soc/tegra: fuse: Add Tegra210 support</title>
<updated>2015-07-16T08:38:29Z</updated>
<author>
<name>Thierry Reding</name>
<email>treding@nvidia.com</email>
</author>
<published>2015-04-29T14:55:57Z</published>
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<id>urn:sha1:0dc5a0d836751099f2e08deec28f56ec881925dd</id>
<content type='text'>
Add Tegra210 support to the fuses driver and add Tegra210-specific
speedo definitions.

Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>soc/tegra: fuse: Add RAM code reader helper</title>
<updated>2015-05-04T12:21:21Z</updated>
<author>
<name>Mikko Perttunen</name>
<email>mperttunen@nvidia.com</email>
</author>
<published>2015-03-12T14:47:55Z</published>
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<id>urn:sha1:6ea2609ab386f6bfeebc39e1418b7497a9deb55c</id>
<content type='text'>
Needed for the EMC and MC drivers to know what timings from the DT to
use.

Signed-off-by: Mikko Perttunen &lt;mperttunen@nvidia.com&gt;
Signed-off-by: Tomeu Vizoso &lt;tomeu.vizoso@collabora.com&gt;
Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>soc/tegra: Add Tegra132 support</title>
<updated>2015-01-09T15:13:57Z</updated>
<author>
<name>Thierry Reding</name>
<email>treding@nvidia.com</email>
</author>
<published>2015-01-08T07:24:45Z</published>
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<id>urn:sha1:24ef5745dafc2eaf287a0bb9ee9e4ff9a4f64108</id>
<content type='text'>
Add the chip ID for the NVIDIA Tegra132 SoC family.

Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>soc/tegra: fuse: Set up in early initcall</title>
<updated>2014-07-17T12:58:42Z</updated>
<author>
<name>Thierry Reding</name>
<email>treding@nvidia.com</email>
</author>
<published>2014-07-11T09:13:30Z</published>
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<id>urn:sha1:24fa5af81059af90c723bec6aacc3cd2b2809d14</id>
<content type='text'>
Rather than rely on explicit initialization order called from SoC setup
code, use a plain initcall and rely on initcall ordering to take care of
dependencies.

This driver exposes some functionality (querying the chip ID) needed at
very early stages of the boot process. An early initcall is good enough
provided that some of the dependencies are deferred to later stages. To
make sure any abuses are easily caught, output a warning message if the
chip ID is queried while it can't be read yet.

Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>soc/tegra: fuse: move APB DMA into Tegra20 fuse driver</title>
<updated>2014-07-17T12:37:12Z</updated>
<author>
<name>Peter De Schrijver</name>
<email>pdeschrijver@nvidia.com</email>
</author>
<published>2014-06-12T15:36:40Z</published>
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<id>urn:sha1:0d827a4343b596b71a1741328c4e5687ce654e19</id>
<content type='text'>
The Tegra20 fuse driver is the only user of tegra_apb_readl_using_dma().
Therefore we can simply the code by incorporating the APB DMA handling into
the driver directly. tegra_apb_writel_using_dma() is dropped because there
are no users.

Signed-off-by: Peter De Schrijver &lt;pdeschrijver@nvidia.com&gt;
Signed-off-by: Stephen Warren &lt;swarren@nvidia.com&gt;
Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>soc/tegra: Add efuse driver for Tegra</title>
<updated>2014-07-17T12:36:01Z</updated>
<author>
<name>Peter De Schrijver</name>
<email>pdeschrijver@nvidia.com</email>
</author>
<published>2014-06-12T15:36:37Z</published>
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<id>urn:sha1:783c8f4c84451bc444e314a71b447239c6ef6fd9</id>
<content type='text'>
Implement fuse driver for Tegra20, Tegra30, Tegra114 and Tegra124. This
replaces functionality previously provided in arch/arm/mach-tegra, which
is removed in this patch.

While at it, move the only user of the global tegra_revision variable
over to tegra_sku_info.revision and export tegra_fuse_readl() to allow
drivers to read calibration fuses.

Signed-off-by: Peter De Schrijver &lt;pdeschrijver@nvidia.com&gt;
Signed-off-by: Stephen Warren &lt;swarren@nvidia.com&gt;
Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>ARM: tegra: move fuse exports to soc/tegra/fuse.h</title>
<updated>2014-07-17T12:32:51Z</updated>
<author>
<name>Peter De Schrijver</name>
<email>pdeschrijver@nvidia.com</email>
</author>
<published>2014-06-12T15:36:36Z</published>
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<id>urn:sha1:35874f3617b38e0c1f72163407c41d554a8f5939</id>
<content type='text'>
All fuse related functionality will move to a driver in the following
patches. To prepare for this, export all the required functionality in a
global header file and move all users of fuse.h to soc/tegra/fuse.h.

While we're at it, remove tegra_bct_strapping, as its only user was
removed in Commit a7cbe92cef27 ("ARM: tegra: remove tegra EMC scaling
driver").

Signed-off-by: Peter De Schrijver &lt;pdeschrijver@nvidia.com&gt;
Signed-off-by: Stephen Warren &lt;swarren@nvidia.com&gt;
Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
</feed>
