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<title>kernel/include/soc/rockchip/rockchip_grf.h, branch linux-6.18.y</title>
<subtitle>Hosts the 0x221E linux distro kernel.</subtitle>
<id>https://universe.0xinfinity.dev/distro/kernel/atom?h=linux-6.18.y</id>
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<updated>2025-09-09T14:37:39Z</updated>
<entry>
<title>PM / devfreq: rockchip-dfi: add support for LPDDR5</title>
<updated>2025-09-09T14:37:39Z</updated>
<author>
<name>Nicolas Frattaroli</name>
<email>nicolas.frattaroli@collabora.com</email>
</author>
<published>2025-05-30T13:38:09Z</published>
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<id>urn:sha1:eddb5ba91b289faa15117d4fc1c2fb223f3493c2</id>
<content type='text'>
The Rockchip RK3588 SoC can also support LPDDR5 memory. This type of
memory needs some special case handling in the rockchip-dfi driver.

Add support for it in rockchip-dfi, as well as the needed GRF register
definitions.

This has been tested as returning both the right cycle count and
bandwidth on a LPDDR5 board where the CKR bit is 1. I couldn't test
whether the values are correct on a system where CKR is 0, as I'm not
savvy enough with the Rockchip tooling to know whether this can be set
in the DDR init blob.

Downstream has some special case handling for a hardware version where
not just the control bits differ, but also the register. Since I don't
know whether that hardware version is in any production silicon, it's
left unimplemented for now, with an error message urging users to report
if they have such a system.

There is a slight change of behaviour for non-LPDDR5 systems: instead of
writing 0 as the control flags to the control register and pretending
everything is alright if the memory type is unknown, we now explicitly
return an error.

Signed-off-by: Nicolas Frattaroli &lt;nicolas.frattaroli@collabora.com&gt;
Reviewed-by: Sascha Hauer &lt;s.hauer@pengutronix.de&gt;
Acked-by: Heiko Stuebner &lt;heiko@sntech.de&gt;
Signed-off-by: Chanwoo Choi &lt;cw00.choi@samsung.com&gt;
Link: https://patchwork.kernel.org/project/linux-pm/patch/20250530-rk3588-dfi-improvements-v1-2-6e077c243a95@collabora.com/
</content>
</entry>
<entry>
<title>PM / devfreq: rockchip-dfi: Handle LPDDR4X</title>
<updated>2023-10-19T11:48:28Z</updated>
<author>
<name>Sascha Hauer</name>
<email>s.hauer@pengutronix.de</email>
</author>
<published>2023-10-18T06:17:00Z</published>
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<id>urn:sha1:d8c6e337e71d3aa05414d8a06a4ff19d45c7be36</id>
<content type='text'>
In the DFI driver LPDDR4X can be handled in the same way as LPDDR4. Add
the missing case.

Link: https://lore.kernel.org/all/20231018061714.3553817-13-s.hauer@pengutronix.de/
Reviewed-by: Jonathan Cameron &lt;Jonathan.Cameron@huawei.com&gt;
Reviewed-by: Sebastian Reichel &lt;sebastian.reichel@collabora.com&gt;
Acked-by: Chanwoo Choi &lt;cw00.choi@samsung.com&gt;
Acked-by: Heiko Stuebner &lt;heiko@sntech.de&gt;
Signed-off-by: Sascha Hauer &lt;s.hauer@pengutronix.de&gt;
Signed-off-by: Chanwoo Choi &lt;cw00.choi@samsung.com&gt;
</content>
</entry>
<entry>
<title>PM / devfreq: rk3399_dmc,dfi: generalize DDRTYPE defines</title>
<updated>2023-10-19T11:39:08Z</updated>
<author>
<name>Sascha Hauer</name>
<email>s.hauer@pengutronix.de</email>
</author>
<published>2023-10-18T06:16:56Z</published>
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<id>urn:sha1:74002e668d0948d12eb2283891cfbd71be9d53c6</id>
<content type='text'>
The DDRTYPE defines are named to be RK3399 specific, but they can be
used for other Rockchip SoCs as well, so replace the RK3399_PMUGRF_
prefix with ROCKCHIP_. They are defined in a SoC specific header
file, so when generalizing the prefix also move the new defines to
a SoC agnostic header file. While at it use GENMASK to define the
DDRTYPE bitfield and give it a name including the full register name.

Link: https://lore.kernel.org/all/20231018061714.3553817-9-s.hauer@pengutronix.de/
Reviewed-by: Sebastian Reichel &lt;sebastian.reichel@collabora.com&gt;
Acked-by: Chanwoo Choi &lt;cw00.choi@samsung.com&gt;
Acked-by: Heiko Stuebner &lt;heiko@sntech.de&gt;
Signed-off-by: Sascha Hauer &lt;s.hauer@pengutronix.de&gt;
Signed-off-by: Chanwoo Choi &lt;cw00.choi@samsung.com&gt;
</content>
</entry>
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