kernel/include/soc/fsl/qe, branch linux-5.1.y

net/wan/fsl_ucc_hdlc: error counters

2018-10-23T02:58:10Z

Extract error information from rx and tx buffer descriptors, and update error counters. Signed-off-by: Mathias Thore Signed-off-by: David S. Miller

net/wan/fsl_ucc_hdlc: add hdlc-bus support

2017-05-18T14:28:39Z

This adds support for hdlc-bus mode to the fsl_ucc_hdlc driver. This can be enabled with the "fsl,hdlc-bus" property in the DTS node of the corresponding ucc. This aligns the configuration of the UPSMR and GUMR registers to what is done in our ucc_hdlc driver (that only support hdlc-bus mode) and with the QuickEngine's documentation for hdlc-bus mode. GUMR/SYNL is set to AUTO for the busmode as in this case the CD signal is ignored. The brkpt_support is enabled to set the HBM1 bit in the CMXUCR register to configure an open-drain connected HDLC bus. Signed-off-by: Holger Brunck Cc: Zhao Qiang Signed-off-by: David S. Miller

fsl/qe: add bit description for SYNL register for GUMR

2017-05-18T14:28:39Z

Add the bitmask for the two bit SYNL register according to the QUICK Engine Reference Manual. Signed-off-by: Holger Brunck Cc: Zhao Qiang Signed-off-by: David S. Miller

soc/fsl/qe: get rid of immrbar_virt_to_phys()

2017-04-30T06:26:54Z

immrbar_virt_to_phys() is not used anymore Signed-off-by: Christophe Leroy Acked-by: Li Yang Signed-off-by: Scott Wood

net: ethernet: ucc_geth: fix MEM_PART_MURAM mode

2017-04-30T06:26:32Z

Since commit 5093bb965a163 ("powerpc/QE: switch to the cpm_muram implementation"), muram area is not part of immrbar mapping anymore so immrbar_virt_to_phys() is not usable anymore. Fixes: 5093bb965a163 ("powerpc/QE: switch to the cpm_muram implementation") Signed-off-by: Christophe Leroy Acked-by: David S. Miller Acked-by: Li Yang Signed-off-by: Scott Wood

fsl/qe: Do not prefix header guard with CONFIG_

2016-06-08T18:08:01Z

The CONFIG_ prefix should only be used for options which can be configured through Kconfig and not for guarding headers. Signed-off-by: Andreas Ziegler Signed-off-by: David S. Miller

drivers/net: support hdlc function for QE-UCC

2016-06-07T22:56:31Z

The driver add hdlc support for Freescale QUICC Engine. It support NMSI and TSA mode. Signed-off-by: Zhao Qiang Signed-off-by: David S. Miller

fsl/qe: Add QE TDM lib

2016-06-07T22:56:31Z

QE has module to support TDM, some other protocols supported by QE are based on TDM. add a qe-tdm lib, this lib provides functions to the protocols using TDM to configurate QE-TDM. Signed-off-by: Zhao Qiang Signed-off-by: David S. Miller

fsl/qe: Make regs resouce_size_t

2016-06-07T22:56:31Z

Signed-off-by: Zhao Qiang Signed-off-by: David S. Miller

fsl/qe: setup clock source for TDM mode

2016-06-07T22:56:30Z

Add tdm clock configuration in both qe clock system and ucc fast controller. Signed-off-by: Zhao Qiang Signed-off-by: David S. Miller