<feed xmlns='http://www.w3.org/2005/Atom'>
<title>kernel/include/linux/soc/mediatek/infracfg.h, branch linux-6.18.y</title>
<subtitle>Hosts the 0x221E linux distro kernel.</subtitle>
<id>https://universe.0xinfinity.dev/distro/kernel/atom?h=linux-6.18.y</id>
<link rel='self' href='https://universe.0xinfinity.dev/distro/kernel/atom?h=linux-6.18.y'/>
<link rel='alternate' type='text/html' href='https://universe.0xinfinity.dev/distro/kernel/'/>
<updated>2024-10-22T11:08:11Z</updated>
<entry>
<title>pmdomain: mediatek: Add support for MT6735</title>
<updated>2024-10-22T11:08:11Z</updated>
<author>
<name>Yassine Oudjana</name>
<email>y.oudjana@protonmail.com</email>
</author>
<published>2024-10-17T08:51:35Z</published>
<link rel='alternate' type='text/html' href='https://universe.0xinfinity.dev/distro/kernel/commit/?id=c2114a0d17631497df99388905353c11f4d5f0dd'/>
<id>urn:sha1:c2114a0d17631497df99388905353c11f4d5f0dd</id>
<content type='text'>
Add support for SCPSYS power domains of MT6735. All non-CPU power domains
are added except for MD2 (C2K modem), which is left out due to issues
with powering it on.

Signed-off-by: Yassine Oudjana &lt;y.oudjana@protonmail.com&gt;
Reviewed-by: AngeloGioacchino Del Regno &lt;angelogioacchino.delregno@collabora.com&gt;
Link: https://lore.kernel.org/r/20241017085136.68053-3-y.oudjana@protonmail.com
Signed-off-by: Ulf Hansson &lt;ulf.hansson@linaro.org&gt;
</content>
</entry>
<entry>
<title>pmdomain: mediatek: Add support for MT8365</title>
<updated>2023-10-17T09:41:42Z</updated>
<author>
<name>Fabien Parent</name>
<email>fparent@baylibre.com</email>
</author>
<published>2023-09-18T09:37:52Z</published>
<link rel='alternate' type='text/html' href='https://universe.0xinfinity.dev/distro/kernel/commit/?id=c5b5831f3c168a1bf1172159c4956e721a0064cf'/>
<id>urn:sha1:c5b5831f3c168a1bf1172159c4956e721a0064cf</id>
<content type='text'>
Add the needed board data to support MT8365 SoC.

Signed-off-by: Fabien Parent &lt;fparent@baylibre.com&gt;
Signed-off-by: Markus Schneider-Pargmann &lt;msp@baylibre.com&gt;
Reviewed-by: AngeloGioacchino Del Regno &lt;angelogioacchino.delregno@collabora.com&gt;
Reviewed-by: Alexandre Mergnat &lt;amergnat@baylibre.com&gt;
Tested-by: Alexandre Mergnat &lt;amergnat@baylibre.com&gt;
Link: https://lore.kernel.org/r/20230918093751.1188668-9-msp@baylibre.com
Signed-off-by: Ulf Hansson &lt;ulf.hansson@linaro.org&gt;
</content>
</entry>
<entry>
<title>soc: mediatek: pm-domains: Add support for mt8188</title>
<updated>2023-01-19T16:17:37Z</updated>
<author>
<name>Garmin.Chang</name>
<email>Garmin.Chang@mediatek.com</email>
</author>
<published>2022-12-23T08:05:53Z</published>
<link rel='alternate' type='text/html' href='https://universe.0xinfinity.dev/distro/kernel/commit/?id=e610e81464e4e52645a0f5d259b8a9e3632db6ff'/>
<id>urn:sha1:e610e81464e4e52645a0f5d259b8a9e3632db6ff</id>
<content type='text'>
Add domain control data including bus protection data size
change due to more protection steps in mt8188.

Signed-off-by: Garmin.Chang &lt;Garmin.Chang@mediatek.com&gt;
Reviewed-by: AngeloGioacchino Del Regno &lt;angelogioacchino.delregno@collabora.com&gt;
Link: https://lore.kernel.org/r/20221223080553.9397-3-Garmin.Chang@mediatek.com
Signed-off-by: Matthias Brugger &lt;matthias.bgg@gmail.com&gt;
</content>
</entry>
<entry>
<title>soc: mediatek: mtk-infracfg: Disable ACP on MT8192</title>
<updated>2022-03-01T07:21:28Z</updated>
<author>
<name>Alyssa Rosenzweig</name>
<email>alyssa.rosenzweig@collabora.com</email>
</author>
<published>2022-02-15T18:46:51Z</published>
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<id>urn:sha1:dcfd5192563909219f6304b4e3e10db071158eef</id>
<content type='text'>
MT8192 contains an experimental Accelerator Coherency Port
implementation, which does not work correctly but was unintentionally
enabled by default. For correct operation of the GPU, we must set a
chicken bit disabling ACP on MT8192.

Adapted from the following downstream change to the out-of-tree, legacy
Mali GPU driver:

https://chromium-review.googlesource.com/c/chromiumos/third_party/kernel/+/2781271/5

Note this change is required for both Panfrost and the legacy kernel
driver.

Co-developed-by: Robin Murphy &lt;robin.murphy@arm.com&gt;
Signed-off-by: Robin Murphy &lt;robin.murphy@arm.com&gt;
Signed-off-by: Alyssa Rosenzweig &lt;alyssa.rosenzweig@collabora.com&gt;
Cc: Nick Fan &lt;Nick.Fan@mediatek.com&gt;
Cc: Nicolas Boichat &lt;drinkcat@chromium.org&gt;
Cc: Chen-Yu Tsai &lt;wenst@chromium.org&gt;
Cc: Stephen Boyd &lt;sboyd@kernel.org&gt;
Cc: AngeloGioacchino Del Regno &lt;angelogioacchino.delregno@collabora.com&gt;
Tested-by: AngeloGioacchino Del Regno &lt;angelogioacchino.delregno@collabora.com&gt;
Link: https://lore.kernel.org/r/20220215184651.12168-1-alyssa.rosenzweig@collabora.com
Signed-off-by: Matthias Brugger &lt;matthias.bgg@gmail.com&gt;
</content>
</entry>
<entry>
<title>soc: mediatek: pm-domains: Add support for mt8186</title>
<updated>2022-02-28T11:02:11Z</updated>
<author>
<name>Chun-Jie Chen</name>
<email>chun-jie.chen@mediatek.com</email>
</author>
<published>2022-02-15T10:49:17Z</published>
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<id>urn:sha1:88590cbc17033c86c8591d9f22401325961a8a59</id>
<content type='text'>
Add power domain control data in mt8186.

Signed-off-by: Chun-Jie Chen &lt;chun-jie.chen@mediatek.com&gt;
Link: https://lore.kernel.org/r/20220215104917.5726-3-chun-jie.chen@mediatek.com
Signed-off-by: Matthias Brugger &lt;matthias.bgg@gmail.com&gt;
</content>
</entry>
<entry>
<title>soc: mediatek: pm-domains: Add support for mt8195</title>
<updated>2022-02-28T11:02:04Z</updated>
<author>
<name>Chun-Jie Chen</name>
<email>chun-jie.chen@mediatek.com</email>
</author>
<published>2022-01-30T01:21:04Z</published>
<link rel='alternate' type='text/html' href='https://universe.0xinfinity.dev/distro/kernel/commit/?id=342479c86d3e8f9e946a07ff0cafbd36511ae30a'/>
<id>urn:sha1:342479c86d3e8f9e946a07ff0cafbd36511ae30a</id>
<content type='text'>
Add domain control data including bus protection data size
change due to more protection steps in mt8195.

Signed-off-by: Chun-Jie Chen &lt;chun-jie.chen@mediatek.com&gt;
Reviewed-by: Chen-Yu Tsai &lt;wenst@chromium.org&gt;
Reviewed-by: AngeloGioacchino Del Regno &lt;angelogioacchino.delregno@collabora.com&gt;
Link: https://lore.kernel.org/r/20220130012104.5292-6-chun-jie.chen@mediatek.com
Signed-off-by: Matthias Brugger &lt;matthias.bgg@gmail.com&gt;
</content>
</entry>
<entry>
<title>soc: mediatek: pm-domains: Add support for mt8167</title>
<updated>2021-01-31T10:19:30Z</updated>
<author>
<name>Fabien Parent</name>
<email>fparent@baylibre.com</email>
</author>
<published>2020-12-09T13:32:37Z</published>
<link rel='alternate' type='text/html' href='https://universe.0xinfinity.dev/distro/kernel/commit/?id=207f13b419a60c56fb75baeb3d668de080514354'/>
<id>urn:sha1:207f13b419a60c56fb75baeb3d668de080514354</id>
<content type='text'>
Add the needed board data to support mt8167 SoC.

Signed-off-by: Fabien Parent &lt;fparent@baylibre.com&gt;
Reviewed-by: Enric Balletbo i Serra &lt;enric.balletbo@collabora.com&gt;
Link: https://lore.kernel.org/r/20201209133238.384030-2-fparent@baylibre.com
Signed-off-by: Matthias Brugger &lt;matthias.bgg@gmail.com&gt;
</content>
</entry>
<entry>
<title>soc: mediatek: pm-domains: Add support for mt8192</title>
<updated>2020-11-27T11:04:43Z</updated>
<author>
<name>Weiyi Lu</name>
<email>weiyi.lu@mediatek.com</email>
</author>
<published>2020-10-30T11:36:22Z</published>
<link rel='alternate' type='text/html' href='https://universe.0xinfinity.dev/distro/kernel/commit/?id=a49d5e7a89d644a5c0ddc851be4bbf08614e6015'/>
<id>urn:sha1:a49d5e7a89d644a5c0ddc851be4bbf08614e6015</id>
<content type='text'>
Add the needed board data to support mt8192 SoC.

Signed-off-by: Weiyi Lu &lt;weiyi.lu@mediatek.com&gt;
Signed-off-by: Enric Balletbo i Serra &lt;enric.balletbo@collabora.com&gt;
Tested-by: Weiyi Lu &lt;weiyi.lu@mediatek.com&gt;
Link: https://lore.kernel.org/r/20201030113622.201188-17-enric.balletbo@collabora.com
Signed-off-by: Matthias Brugger &lt;matthias.bgg@gmail.com&gt;
</content>
</entry>
<entry>
<title>soc: mediatek: pm-domains: Add support for mt8183</title>
<updated>2020-11-27T11:04:43Z</updated>
<author>
<name>Matthias Brugger</name>
<email>mbrugger@suse.com</email>
</author>
<published>2020-10-30T11:36:17Z</published>
<link rel='alternate' type='text/html' href='https://universe.0xinfinity.dev/distro/kernel/commit/?id=eb9fa767fbe19d3db7d303e9fde7f3056221ffe1'/>
<id>urn:sha1:eb9fa767fbe19d3db7d303e9fde7f3056221ffe1</id>
<content type='text'>
Add the needed board data to support mt8183 SoC.

Signed-off-by: Matthias Brugger &lt;mbrugger@suse.com&gt;
Signed-off-by: Enric Balletbo i Serra &lt;enric.balletbo@collabora.com&gt;
Link: https://lore.kernel.org/r/20201030113622.201188-12-enric.balletbo@collabora.com
Signed-off-by: Matthias Brugger &lt;matthias.bgg@gmail.com&gt;
</content>
</entry>
<entry>
<title>soc: mediatek: pm_domains: Make bus protection generic</title>
<updated>2020-11-27T11:04:42Z</updated>
<author>
<name>Matthias Brugger</name>
<email>mbrugger@suse.com</email>
</author>
<published>2020-10-30T11:36:11Z</published>
<link rel='alternate' type='text/html' href='https://universe.0xinfinity.dev/distro/kernel/commit/?id=928296ea5da37838d7127de4b10f47cd97401b13'/>
<id>urn:sha1:928296ea5da37838d7127de4b10f47cd97401b13</id>
<content type='text'>
Bus protection is not exclusively done by calling the infracfg misc driver.
Make the calls for setting and clearing the bus protection generic so
that we can use other blocks for it as well.

Signed-off-by: Matthias Brugger &lt;mbrugger@suse.com&gt;
Signed-off-by: Enric Balletbo i Serra &lt;enric.balletbo@collabora.com&gt;
Link: https://lore.kernel.org/r/20201030113622.201188-6-enric.balletbo@collabora.com
Signed-off-by: Matthias Brugger &lt;matthias.bgg@gmail.com&gt;
</content>
</entry>
</feed>
