<feed xmlns='http://www.w3.org/2005/Atom'>
<title>kernel/include/linux/soc/mediatek/infracfg.h, branch linux-6.1.y</title>
<subtitle>Hosts the 0x221E linux distro kernel.</subtitle>
<id>https://universe.0xinfinity.dev/distro/kernel/atom?h=linux-6.1.y</id>
<link rel='self' href='https://universe.0xinfinity.dev/distro/kernel/atom?h=linux-6.1.y'/>
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<updated>2022-03-01T07:21:28Z</updated>
<entry>
<title>soc: mediatek: mtk-infracfg: Disable ACP on MT8192</title>
<updated>2022-03-01T07:21:28Z</updated>
<author>
<name>Alyssa Rosenzweig</name>
<email>alyssa.rosenzweig@collabora.com</email>
</author>
<published>2022-02-15T18:46:51Z</published>
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<id>urn:sha1:dcfd5192563909219f6304b4e3e10db071158eef</id>
<content type='text'>
MT8192 contains an experimental Accelerator Coherency Port
implementation, which does not work correctly but was unintentionally
enabled by default. For correct operation of the GPU, we must set a
chicken bit disabling ACP on MT8192.

Adapted from the following downstream change to the out-of-tree, legacy
Mali GPU driver:

https://chromium-review.googlesource.com/c/chromiumos/third_party/kernel/+/2781271/5

Note this change is required for both Panfrost and the legacy kernel
driver.

Co-developed-by: Robin Murphy &lt;robin.murphy@arm.com&gt;
Signed-off-by: Robin Murphy &lt;robin.murphy@arm.com&gt;
Signed-off-by: Alyssa Rosenzweig &lt;alyssa.rosenzweig@collabora.com&gt;
Cc: Nick Fan &lt;Nick.Fan@mediatek.com&gt;
Cc: Nicolas Boichat &lt;drinkcat@chromium.org&gt;
Cc: Chen-Yu Tsai &lt;wenst@chromium.org&gt;
Cc: Stephen Boyd &lt;sboyd@kernel.org&gt;
Cc: AngeloGioacchino Del Regno &lt;angelogioacchino.delregno@collabora.com&gt;
Tested-by: AngeloGioacchino Del Regno &lt;angelogioacchino.delregno@collabora.com&gt;
Link: https://lore.kernel.org/r/20220215184651.12168-1-alyssa.rosenzweig@collabora.com
Signed-off-by: Matthias Brugger &lt;matthias.bgg@gmail.com&gt;
</content>
</entry>
<entry>
<title>soc: mediatek: pm-domains: Add support for mt8186</title>
<updated>2022-02-28T11:02:11Z</updated>
<author>
<name>Chun-Jie Chen</name>
<email>chun-jie.chen@mediatek.com</email>
</author>
<published>2022-02-15T10:49:17Z</published>
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<id>urn:sha1:88590cbc17033c86c8591d9f22401325961a8a59</id>
<content type='text'>
Add power domain control data in mt8186.

Signed-off-by: Chun-Jie Chen &lt;chun-jie.chen@mediatek.com&gt;
Link: https://lore.kernel.org/r/20220215104917.5726-3-chun-jie.chen@mediatek.com
Signed-off-by: Matthias Brugger &lt;matthias.bgg@gmail.com&gt;
</content>
</entry>
<entry>
<title>soc: mediatek: pm-domains: Add support for mt8195</title>
<updated>2022-02-28T11:02:04Z</updated>
<author>
<name>Chun-Jie Chen</name>
<email>chun-jie.chen@mediatek.com</email>
</author>
<published>2022-01-30T01:21:04Z</published>
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<id>urn:sha1:342479c86d3e8f9e946a07ff0cafbd36511ae30a</id>
<content type='text'>
Add domain control data including bus protection data size
change due to more protection steps in mt8195.

Signed-off-by: Chun-Jie Chen &lt;chun-jie.chen@mediatek.com&gt;
Reviewed-by: Chen-Yu Tsai &lt;wenst@chromium.org&gt;
Reviewed-by: AngeloGioacchino Del Regno &lt;angelogioacchino.delregno@collabora.com&gt;
Link: https://lore.kernel.org/r/20220130012104.5292-6-chun-jie.chen@mediatek.com
Signed-off-by: Matthias Brugger &lt;matthias.bgg@gmail.com&gt;
</content>
</entry>
<entry>
<title>soc: mediatek: pm-domains: Add support for mt8167</title>
<updated>2021-01-31T10:19:30Z</updated>
<author>
<name>Fabien Parent</name>
<email>fparent@baylibre.com</email>
</author>
<published>2020-12-09T13:32:37Z</published>
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<id>urn:sha1:207f13b419a60c56fb75baeb3d668de080514354</id>
<content type='text'>
Add the needed board data to support mt8167 SoC.

Signed-off-by: Fabien Parent &lt;fparent@baylibre.com&gt;
Reviewed-by: Enric Balletbo i Serra &lt;enric.balletbo@collabora.com&gt;
Link: https://lore.kernel.org/r/20201209133238.384030-2-fparent@baylibre.com
Signed-off-by: Matthias Brugger &lt;matthias.bgg@gmail.com&gt;
</content>
</entry>
<entry>
<title>soc: mediatek: pm-domains: Add support for mt8192</title>
<updated>2020-11-27T11:04:43Z</updated>
<author>
<name>Weiyi Lu</name>
<email>weiyi.lu@mediatek.com</email>
</author>
<published>2020-10-30T11:36:22Z</published>
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<id>urn:sha1:a49d5e7a89d644a5c0ddc851be4bbf08614e6015</id>
<content type='text'>
Add the needed board data to support mt8192 SoC.

Signed-off-by: Weiyi Lu &lt;weiyi.lu@mediatek.com&gt;
Signed-off-by: Enric Balletbo i Serra &lt;enric.balletbo@collabora.com&gt;
Tested-by: Weiyi Lu &lt;weiyi.lu@mediatek.com&gt;
Link: https://lore.kernel.org/r/20201030113622.201188-17-enric.balletbo@collabora.com
Signed-off-by: Matthias Brugger &lt;matthias.bgg@gmail.com&gt;
</content>
</entry>
<entry>
<title>soc: mediatek: pm-domains: Add support for mt8183</title>
<updated>2020-11-27T11:04:43Z</updated>
<author>
<name>Matthias Brugger</name>
<email>mbrugger@suse.com</email>
</author>
<published>2020-10-30T11:36:17Z</published>
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<id>urn:sha1:eb9fa767fbe19d3db7d303e9fde7f3056221ffe1</id>
<content type='text'>
Add the needed board data to support mt8183 SoC.

Signed-off-by: Matthias Brugger &lt;mbrugger@suse.com&gt;
Signed-off-by: Enric Balletbo i Serra &lt;enric.balletbo@collabora.com&gt;
Link: https://lore.kernel.org/r/20201030113622.201188-12-enric.balletbo@collabora.com
Signed-off-by: Matthias Brugger &lt;matthias.bgg@gmail.com&gt;
</content>
</entry>
<entry>
<title>soc: mediatek: pm_domains: Make bus protection generic</title>
<updated>2020-11-27T11:04:42Z</updated>
<author>
<name>Matthias Brugger</name>
<email>mbrugger@suse.com</email>
</author>
<published>2020-10-30T11:36:11Z</published>
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<id>urn:sha1:928296ea5da37838d7127de4b10f47cd97401b13</id>
<content type='text'>
Bus protection is not exclusively done by calling the infracfg misc driver.
Make the calls for setting and clearing the bus protection generic so
that we can use other blocks for it as well.

Signed-off-by: Matthias Brugger &lt;mbrugger@suse.com&gt;
Signed-off-by: Enric Balletbo i Serra &lt;enric.balletbo@collabora.com&gt;
Link: https://lore.kernel.org/r/20201030113622.201188-6-enric.balletbo@collabora.com
Signed-off-by: Matthias Brugger &lt;matthias.bgg@gmail.com&gt;
</content>
</entry>
<entry>
<title>iommu/mediatek: Check 4GB mode by reading infracfg</title>
<updated>2020-09-04T11:20:36Z</updated>
<author>
<name>Miles Chen</name>
<email>miles.chen@mediatek.com</email>
</author>
<published>2020-09-04T10:40:38Z</published>
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<id>urn:sha1:c2c59456e1fcad3f464761c5839399176e3a934a</id>
<content type='text'>
In previous discussion [1] and [2], we found that it is risky to
use max_pfn or totalram_pages to tell if 4GB mode is enabled.

Check 4GB mode by reading infracfg register, remove the usage
of the un-exported symbol max_pfn.

This is a step towards building mtk_iommu as a kernel module.

[1] https://lore.kernel.org/lkml/20200603161132.2441-1-miles.chen@mediatek.com/
[2] https://lore.kernel.org/lkml/20200604080120.2628-1-miles.chen@mediatek.com/
[3] https://lore.kernel.org/lkml/20200715205120.GA778876@bogus/

Cc: Mike Rapoport &lt;rppt@linux.ibm.com&gt;
Cc: David Hildenbrand &lt;david@redhat.com&gt;
Cc: Yong Wu &lt;yong.wu@mediatek.com&gt;
Cc: Yingjoe Chen &lt;yingjoe.chen@mediatek.com&gt;
Cc: Christoph Hellwig &lt;hch@lst.de&gt;
Cc: Rob Herring &lt;robh@kernel.org&gt;
Cc: Matthias Brugger &lt;matthias.bgg@gmail.com&gt;
Cc: Joerg Roedel &lt;joro@8bytes.org&gt;
Reviewed-by: Matthias Brugger &lt;matthias.bgg@gmail.com&gt;
Signed-off-by: Miles Chen &lt;miles.chen@mediatek.com&gt;
Link: https://lore.kernel.org/r/20200904104038.4979-1-miles.chen@mediatek.com
Signed-off-by: Joerg Roedel &lt;jroedel@suse.de&gt;
</content>
</entry>
<entry>
<title>soc: mediatek: avoid hardcoded value with bus_prot_mask</title>
<updated>2018-03-11T22:42:57Z</updated>
<author>
<name>Sean Wang</name>
<email>sean.wang@mediatek.com</email>
</author>
<published>2018-02-07T10:22:49Z</published>
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<id>urn:sha1:c59c9c85e36aa09cfd901cc15a0d8d3772c18195</id>
<content type='text'>
use a meaningful definition for bus_prot_mask instead of just hardcoded
for it.

Signed-off-by: Sean Wang &lt;sean.wang@mediatek.com&gt;
Reviewed-by: Ulf Hansson &lt;ulf.hansson@linaro.org&gt;
Signed-off-by: Matthias Brugger &lt;matthias.bgg@gmail.com&gt;
</content>
</entry>
<entry>
<title>soc: mediatek: extend bus protection API</title>
<updated>2017-12-21T10:49:22Z</updated>
<author>
<name>weiyi.lu@mediatek.com</name>
<email>weiyi.lu@mediatek.com</email>
</author>
<published>2017-11-28T07:28:18Z</published>
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<id>urn:sha1:fa7e843a901d4ea6b092fea67406f85e8ec60b22</id>
<content type='text'>
MT2712 add "set/clear" bus control register to each control register set
instead of providing only one "enable" control register, we could avoid
the read-modify-write racing by declaring "bus_prot_reg_update" as "false"
in scp_soc_data or declaring as "true" to use the legacy update method.
By improving the mtk-infracfg bus protection implementation to
support set/clear bus protection control method by IC configuration.

Signed-off-by: Weiyi Lu &lt;weiyi.lu@mediatek.com&gt;
Signed-off-by: Matthias Brugger &lt;matthias.bgg@gmail.com&gt;
</content>
</entry>
</feed>
