<feed xmlns='http://www.w3.org/2005/Atom'>
<title>kernel/include/linux/platform_data/x86/clk-pmc-atom.h, branch linux-5.1.y</title>
<subtitle>Hosts the 0x221E linux distro kernel.</subtitle>
<id>https://universe.0xinfinity.dev/distro/kernel/atom?h=linux-5.1.y</id>
<link rel='self' href='https://universe.0xinfinity.dev/distro/kernel/atom?h=linux-5.1.y'/>
<link rel='alternate' type='text/html' href='https://universe.0xinfinity.dev/distro/kernel/'/>
<updated>2019-04-10T22:54:12Z</updated>
<entry>
<title>clk: x86: Add system specific quirk to mark clocks as critical</title>
<updated>2019-04-10T22:54:12Z</updated>
<author>
<name>David Müller</name>
<email>dave.mueller@gmx.ch</email>
</author>
<published>2019-04-08T13:33:54Z</published>
<link rel='alternate' type='text/html' href='https://universe.0xinfinity.dev/distro/kernel/commit/?id=7c2e07130090ae001a97a6b65597830d6815e93e'/>
<id>urn:sha1:7c2e07130090ae001a97a6b65597830d6815e93e</id>
<content type='text'>
Since commit 648e921888ad ("clk: x86: Stop marking clocks as
CLK_IS_CRITICAL"), the pmc_plt_clocks of the Bay Trail SoC are
unconditionally gated off. Unfortunately this will break systems where these
clocks are used for external purposes beyond the kernel's knowledge. Fix it
by implementing a system specific quirk to mark the necessary pmc_plt_clks as
critical.

Fixes: 648e921888ad ("clk: x86: Stop marking clocks as CLK_IS_CRITICAL")
Signed-off-by: David Müller &lt;dave.mueller@gmx.ch&gt;
Signed-off-by: Hans de Goede &lt;hdegoede@redhat.com&gt;
Reviewed-by: Andy Shevchenko &lt;andy.shevchenko@gmail.com&gt;
Signed-off-by: Stephen Boyd &lt;sboyd@kernel.org&gt;
</content>
</entry>
<entry>
<title>clk: x86: Add Atom PMC platform clocks</title>
<updated>2017-01-27T00:20:46Z</updated>
<author>
<name>Irina Tirdea</name>
<email>irina.tirdea@intel.com</email>
</author>
<published>2017-01-23T18:07:42Z</published>
<link rel='alternate' type='text/html' href='https://universe.0xinfinity.dev/distro/kernel/commit/?id=1141d9d08184565b71a943a50ffe712b2dfc697f'/>
<id>urn:sha1:1141d9d08184565b71a943a50ffe712b2dfc697f</id>
<content type='text'>
The BayTrail and CherryTrail platforms provide platform clocks
through their Power Management Controller (PMC).

The SoC supports up to 6 clocks (PMC_PLT_CLK[0..5]) with a
frequency of either 19.2 MHz (PLL) or 25 MHz (XTAL) for BayTrail
and a frequency of 19.2 MHz (XTAL) for CherryTrail. These clocks
are available for general system use, where appropriate, and each
have Control &amp; Frequency register fields associated with them.

Port from legacy by Pierre Bossart, integration in clock framework
by Irina Tirdea

Signed-off-by: Irina Tirdea &lt;irina.tirdea@intel.com&gt;
Signed-off-by: Pierre-Louis Bossart &lt;pierre-louis.bossart@linux.intel.com&gt;
Acked-by: Andy Shevchenko &lt;andriy.shevchenko@linux.intel.com&gt;
Signed-off-by: Stephen Boyd &lt;sboyd@codeaurora.org&gt;
</content>
</entry>
</feed>
