kernel/include/linux/pci-epc.h, branch linux-5.2.y

PCI: endpoint: Add support to specify alignment for buffers allocated to BARs

2019-04-15T12:24:02Z

The address that is allocated using pci_epf_alloc_space() is directly written to the target address of the Inbound Address Translation unit (ie the HW component implementing inbound address decoding) on endpoint controllers. Designware IP [1] has a configuration parameter (CX_ATU_MIN_REGION_SIZE [2]) which has 64KB as default value and the lower 16 bits of the Base, Limit and Target registers of the Inbound ATU are fixed to zero. If the programmed memory address is not aligned to 64 KB boundary this causes memory corruption. Modify pci_epf_alloc_space() API to take alignment size as argument in order to allocate buffers to be mapped to BARs with an alignment that suits the platform where they are used. Add an 'align' parameter to epc_features which can be used by platform drivers to specify the BAR allocation alignment requirements and use this while invoking pci_epf_alloc_space(). [1] "I/O and MEM Match Modes" section in DesignWare Cores PCI Express Controller Databook version 4.90a [2] http://www.ti.com/lit/ug/spruid7c/spruid7c.pdf Signed-off-by: Kishon Vijay Abraham I Signed-off-by: Lorenzo Pieralisi

PCI: endpoint: Remove features member in struct pci_epc

2019-02-15T10:03:35Z

Since EPC features are now implemented using pci_epc_features and all the EPC drivers are moved to using pci_epc_features, remove features member in struct pci_epc and all the helper macros for configuring the features. Tested-by: Gustavo Pimentel Signed-off-by: Kishon Vijay Abraham I Signed-off-by: Lorenzo Pieralisi

PCI: endpoint: Add helper to get first unreserved BAR

2019-02-15T09:59:40Z

Add a helper function pci_epc_get_first_free_bar() to get the first unreserved BAR that can be used for endpoint function. Tested-by: Gustavo Pimentel Signed-off-by: Kishon Vijay Abraham I Signed-off-by: Lorenzo Pieralisi

PCI: endpoint: Add new pci_epc_ops to get EPC features

2019-02-14T16:08:10Z

Add a new pci_epc_ops ->get_features() to get the features supported by the EPC. Since EPC can provide different features to different functions, the ->get_features() ops takes _func_no_ as an argument. Tested-by: Gustavo Pimentel Signed-off-by: Kishon Vijay Abraham I Signed-off-by: Lorenzo Pieralisi

pci-epf-test/pci_endpoint_test: Add MSI-X support

2018-07-19T10:46:45Z

Add MSI-X support and update driver documentation accordingly. Signed-off-by: Gustavo Pimentel Signed-off-by: Lorenzo Pieralisi Acked-by: Kishon Vijay Abraham I

PCI: Update xxx_pcie_ep_raise_irq() and pci_epc_raise_irq() signatures

2018-07-19T10:34:42Z

Change {cdns, dra7xx, artpec6, dw, rockchip}_pcie_ep_raise_irq() and pci_epc_raise_irq() signature, namely the interrupt_num variable type from u8 to u16 to accommodate 2048 maximum MSI-X interrupts. Signed-off-by: Gustavo Pimentel Signed-off-by: Lorenzo Pieralisi Acked-by: Alan Douglas Acked-by: Shawn Lin Acked-by: Jesper Nilsson Acked-by: Joao Pinto Acked-by: Kishon Vijay Abraham I

PCI: endpoint: Add MSI-X interfaces

2018-07-19T10:34:23Z

Add PCI_EPC_IRQ_MSIX type. Add MSI-X callbacks signatures to the ops structure. Add sysfs interface for set/get MSI-X capability maximum number. Update documentation accordingly. Signed-off-by: Gustavo Pimentel Signed-off-by: Lorenzo Pieralisi Acked-by: Kishon Vijay Abraham I

PCI: dwc: Add support for EP mode

2018-05-15T14:51:38Z

The PCIe controller dual mode is capable of operating in Root Complex (RC) mode as well as EP mode by configuration option. Add EP support to the DesignWare driver on top of RC mode support. Add new property on pci_epc structure which allow to configure pci_epf_test driver accordingly to the controller specific requirements. Signed-off-by: Gustavo Pimentel Signed-off-by: Lorenzo Pieralisi Acked-by: Kishon Vijay Abraham I

PCI: endpoint: Make epc->ops->clear_bar()/pci_epc_clear_bar() take struct *epf_bar

2018-04-03T11:38:05Z

Make epc->ops->clear_bar()/pci_epc_clear_bar() take struct *epf_bar. This is needed so that epc->ops->clear_bar() can clear the BAR pair, if the BAR is 64-bits wide. This also makes it possible for pci_epc_clear_bar() to sanity check the flags. Signed-off-by: Niklas Cassel Signed-off-by: Lorenzo Pieralisi Reviewed-by: Gustavo Pimentel

PCI: endpoint: Simplify epc->ops->set_bar()/pci_epc_set_bar()

2018-04-03T11:23:38Z

Add barno and flags to struct epf_bar. That way we can simplify epc->ops->set_bar()/pci_epc_set_bar() by passing a struct *epf_bar instead of a whole lot of arguments. This is needed so that epc->ops->set_bar() implementations can modify BAR flags. Will be utilized in a succeeding patch. Signed-off-by: Niklas Cassel Signed-off-by: Lorenzo Pieralisi Reviewed-by: Gustavo Pimentel Acked-by: Kishon Vijay Abraham I