<feed xmlns='http://www.w3.org/2005/Atom'>
<title>kernel/include/linux/mtd/spi-nor.h, branch linux-5.11.y</title>
<subtitle>Hosts the 0x221E linux distro kernel.</subtitle>
<id>https://universe.0xinfinity.dev/distro/kernel/atom?h=linux-5.11.y</id>
<link rel='self' href='https://universe.0xinfinity.dev/distro/kernel/atom?h=linux-5.11.y'/>
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<updated>2020-12-07T17:27:28Z</updated>
<entry>
<title>mtd: spi-nor: Fix multiple typos</title>
<updated>2020-12-07T17:27:28Z</updated>
<author>
<name>Jonathan Neuschäfer</name>
<email>j.neuschaefer@gmx.net</email>
</author>
<published>2020-11-30T15:24:15Z</published>
<link rel='alternate' type='text/html' href='https://universe.0xinfinity.dev/distro/kernel/commit/?id=c69942bda5152d764ee7d897d1627d64c7177ea1'/>
<id>urn:sha1:c69942bda5152d764ee7d897d1627d64c7177ea1</id>
<content type='text'>
There are a few typos in comments in the SPI NOR framework; fix them.

Signed-off-by: Jonathan Neuschäfer &lt;j.neuschaefer@gmx.net&gt;
Signed-off-by: Vignesh Raghavendra &lt;vigneshr@ti.com&gt;
Reviewed-by: Tudor Ambarus &lt;tudor.ambarus@microchip.com&gt;
Link: https://lore.kernel.org/r/20201130152416.1283972-1-j.neuschaefer@gmx.net
</content>
</entry>
<entry>
<title>mtd: spi-nor: core: perform a Soft Reset on shutdown</title>
<updated>2020-11-09T06:26:17Z</updated>
<author>
<name>Pratyush Yadav</name>
<email>p.yadav@ti.com</email>
</author>
<published>2020-10-05T15:31:35Z</published>
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<id>urn:sha1:d73ee7534cc537b98b61bfd83dbce5bb12aecb80</id>
<content type='text'>
Perform a Soft Reset on shutdown on flashes that support it so that the
flash can be reset to its initial state and any configurations made by
spi-nor (given that they're only done in volatile registers) will be
reset. This will hand back the flash in pristine state for any further
operations on it.

Signed-off-by: Pratyush Yadav &lt;p.yadav@ti.com&gt;
Signed-off-by: Vignesh Raghavendra &lt;vigneshr@ti.com&gt;
Reviewed-by: Tudor Ambarus &lt;tudor.ambarus@microchip.com&gt;
Link: https://lore.kernel.org/r/20201005153138.6437-13-p.yadav@ti.com
</content>
</entry>
<entry>
<title>mtd: spi-nor: add support for DTR protocol</title>
<updated>2020-11-09T06:26:16Z</updated>
<author>
<name>Pratyush Yadav</name>
<email>p.yadav@ti.com</email>
</author>
<published>2020-10-05T15:31:26Z</published>
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<id>urn:sha1:0e30f47232ab57c685258aa91adc3a3e67bd023e</id>
<content type='text'>
Double Transfer Rate (DTR) is SPI protocol in which data is transferred
on each clock edge as opposed to on each clock cycle. Make
framework-level changes to allow supporting flashes in DTR mode.

Right now, mixed DTR modes are not supported. So, for example a mode
like 4S-4D-4D will not work. All phases need to be either DTR or STR.

The xSPI spec says that "The program commands provide SPI backward
compatible commands for programming data...". So 8D-8D-8D page program
opcodes are populated with using 1S-1S-1S opcodes.

Signed-off-by: Pratyush Yadav &lt;p.yadav@ti.com&gt;
Signed-off-by: Vignesh Raghavendra &lt;vigneshr@ti.com&gt;
Reviewed-by: Tudor Ambarus &lt;tudor.ambarus@microchip.com&gt;
Link: https://lore.kernel.org/r/20201005153138.6437-4-p.yadav@ti.com
</content>
</entry>
<entry>
<title>mtd: spi-nor: Fix SPI NOR acronym</title>
<updated>2020-05-28T07:46:23Z</updated>
<author>
<name>Tudor Ambarus</name>
<email>tudor.ambarus@microchip.com</email>
</author>
<published>2020-04-28T08:47:43Z</published>
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<id>urn:sha1:1ac71ec0130cce5bed3ec11ffc88651097a24173</id>
<content type='text'>
The correct terminology is serial NOR flash or SPI NOR.
s/SPI-NOR/SPI NOR and s/spi-nor/SPI NOR across the subsystem.

Signed-off-by: Tudor Ambarus &lt;tudor.ambarus@microchip.com&gt;
Reviewed-by: Sergei Shtylyov &lt;sergei.shtylyov@cogentembedded.com&gt;
</content>
</entry>
<entry>
<title>mtd: spi-nor: fix kernel-doc for spi_nor::spimem</title>
<updated>2020-04-28T06:55:50Z</updated>
<author>
<name>Sergei Shtylyov</name>
<email>sergei.shtylyov@cogentembedded.com</email>
</author>
<published>2020-04-03T20:50:57Z</published>
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<id>urn:sha1:1f241ad2a093b889122bd6bfdce57551d21bba5b</id>
<content type='text'>
When adding the 'spimem' field to 'struct spi_nor', a grammar mistake
("point" instead of "pointer") was made -- fix it and convert the SPI
acronym to uppercase and fully spell out "memory", while at it...

Fixes: b35b9a10362 ("mtd: spi-nor: Move m25p80 code in spi-nor.c")
Signed-off-by: Sergei Shtylyov &lt;sergei.shtylyov@cogentembedded.com&gt;
Signed-off-by: Tudor Ambarus &lt;tudor.ambarus@microchip.com&gt;
</content>
</entry>
<entry>
<title>mtd: spi-nor: fix kernel-doc for spi_nor::info</title>
<updated>2020-04-28T06:55:29Z</updated>
<author>
<name>Sergei Shtylyov</name>
<email>sergei.shtylyov@cogentembedded.com</email>
</author>
<published>2020-04-03T20:49:48Z</published>
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<id>urn:sha1:80cb801144265866ce29fabe5ea7ac8588aa673c</id>
<content type='text'>
When adding the 'info' field to 'struct spi_nor', some acronyms were in
lower case and some in upper case and the JEDEC acronym mistyped -- fix
these issues.

Fixes: 46dde01f6bab ("mtd: spi-nor: add spi_nor_init() function")
Signed-off-by: Sergei Shtylyov &lt;sergei.shtylyov@cogentembedded.com&gt;
Signed-off-by: Tudor Ambarus &lt;tudor.ambarus@microchip.com&gt;
</content>
</entry>
<entry>
<title>mtd: spi-nor: fix kernel-doc for spi_nor::reg_proto</title>
<updated>2020-04-28T06:45:05Z</updated>
<author>
<name>Sergei Shtylyov</name>
<email>sergei.shtylyov@cogentembedded.com</email>
</author>
<published>2020-04-03T20:45:49Z</published>
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<id>urn:sha1:ba053dd3b4d841e17e910d0b91e22d9ea813fa39</id>
<content type='text'>
When adding the '{read|write|reg}_proto' fields to 'struct spi_nor', a
colon was missed in the comment for the spi_nor::reg_proto' -- add it.

Fixes: cfc5604c488c ("mtd: spi-nor: introduce SPI 1-2-2 and SPI 1-4-4 protocols")
Signed-off-by: Sergei Shtylyov &lt;sergei.shtylyov@cogentembedded.com&gt;
Signed-off-by: Tudor Ambarus &lt;tudor.ambarus@microchip.com&gt;
</content>
</entry>
<entry>
<title>mtd: spi-nor: fix kernel-doc for spi_nor::mtd</title>
<updated>2020-04-28T06:45:04Z</updated>
<author>
<name>Sergei Shtylyov</name>
<email>sergei.shtylyov@cogentembedded.com</email>
</author>
<published>2020-04-03T20:44:16Z</published>
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<id>urn:sha1:ba0aa311b0eb9d0a66a1b6b6fdeaa3b7584b798a</id>
<content type='text'>
When embedding 'struct mtd_info' within 'struct spi_nor', the kernel-doc
comment was forgotten. Fix it by dropping the "pointer to" part from the
comment.

Fixes: 1976367173a4 ("mtd: spi-nor: embed struct mtd_info within struct spi_nor")
Signed-off-by: Sergei Shtylyov &lt;sergei.shtylyov@cogentembedded.com&gt;
Signed-off-by: Tudor Ambarus &lt;tudor.ambarus@microchip.com&gt;
</content>
</entry>
<entry>
<title>mtd: spi-nor: fix kernel-doc for 'struct spi_nor'</title>
<updated>2020-04-28T06:45:04Z</updated>
<author>
<name>Sergei Shtylyov</name>
<email>sergei.shtylyov@cogentembedded.com</email>
</author>
<published>2020-04-03T20:41:27Z</published>
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<id>urn:sha1:40a571bc408bf10ac8be0eadf838483b9cf90141</id>
<content type='text'>
When introducing 'struct spi_nor', a number of issues was added in its
kernel-doc comment:

- double article in the heading kernel-doc comment;
- "point" instead of "pointer" for the 'mtd' and 'dev' fields;
- "a" articles instead of "an" for the 'dev' field;
- acronyms in the lower case for the 'dev' field;
- missing "pointer to" for the 'priv' field.

Fix all of those at once...

Fixes: 6e602ef73334 ("mtd: spi-nor: add the basic data structures")
Signed-off-by: Sergei Shtylyov &lt;sergei.shtylyov@cogentembedded.com&gt;
Signed-off-by: Tudor Ambarus &lt;tudor.ambarus@microchip.com&gt;
</content>
</entry>
<entry>
<title>mtd: spi-nor: move #define SPINOR_OP_WRDI</title>
<updated>2020-04-20T09:21:17Z</updated>
<author>
<name>Sergei Shtylyov</name>
<email>sergei.shtylyov@cogentembedded.com</email>
</author>
<published>2020-04-07T20:56:43Z</published>
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<id>urn:sha1:bb15aded5144d36b2a050e1dad415876c0b94234</id>
<content type='text'>
The write disable (WRDI) opcode is not really specific to the SST flashes
(anymore?) -- move the #define to the main opcode group, just before WREN.

Signed-off-by: Sergei Shtylyov &lt;sergei.shtylyov@cogentembedded.com&gt;
Signed-off-by: Tudor Ambarus &lt;tudor.ambarus@microchip.com&gt;
</content>
</entry>
</feed>
