<feed xmlns='http://www.w3.org/2005/Atom'>
<title>kernel/include/linux/mmc, branch linux-6.14.y</title>
<subtitle>Hosts the 0x221E linux distro kernel.</subtitle>
<id>https://universe.0xinfinity.dev/distro/kernel/atom?h=linux-6.14.y</id>
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<updated>2024-12-19T13:43:28Z</updated>
<entry>
<title>mmc: crypto: add mmc_from_crypto_profile()</title>
<updated>2024-12-19T13:43:28Z</updated>
<author>
<name>Eric Biggers</name>
<email>ebiggers@google.com</email>
</author>
<published>2024-12-13T04:19:49Z</published>
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<id>urn:sha1:08a7ead3242f70f4415232800104ae458fd96d17</id>
<content type='text'>
Add a helper function that encapsulates a container_of expression.  For
now there is just one user but soon there will be more.

Signed-off-by: Eric Biggers &lt;ebiggers@google.com&gt;
Message-ID: &lt;20241213041958.202565-7-ebiggers@kernel.org&gt;
Signed-off-by: Ulf Hansson &lt;ulf.hansson@linaro.org&gt;
</content>
</entry>
<entry>
<title>mmc: core: Introduce the MMC_RSP_R1B_NO_CRC response</title>
<updated>2024-12-10T10:18:45Z</updated>
<author>
<name>Andy-ld Lu</name>
<email>andy-ld.lu@mediatek.com</email>
</author>
<published>2024-11-26T12:48:22Z</published>
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<id>urn:sha1:ed97550d470d00ebafe9de888fd100cb82d3abb6</id>
<content type='text'>
The R1B response type with ignoring CRC is used in the mmc_cqe_recovery(),
introduce the MMC_RSP_R1B_NO_CRC response type to simplify the code.

Signed-off-by: Andy-ld Lu &lt;andy-ld.lu@mediatek.com&gt;
Message-ID: &lt;20241126125041.16071-2-andy-ld.lu@mediatek.com&gt;
Signed-off-by: Ulf Hansson &lt;ulf.hansson@linaro.org&gt;
</content>
</entry>
<entry>
<title>mmc: core: Drop the MMC_RSP_R1_NO_CRC response</title>
<updated>2024-12-10T10:18:45Z</updated>
<author>
<name>Ulf Hansson</name>
<email>ulf.hansson@linaro.org</email>
</author>
<published>2024-11-25T13:23:11Z</published>
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<id>urn:sha1:ea79df10331218b04d90f028a605f33c879c518d</id>
<content type='text'>
The MMC_RSP_R1_NO_CRC type of response is not being used by the mmc core
for any commands. Let's therefore drop it, together with the corresponding
code in the host drivers.

Signed-off-by: Ulf Hansson &lt;ulf.hansson@linaro.org&gt;
Acked-by: Wolfram Sang &lt;wsa+renesas@sang-engineering.com&gt; # for TMIO
Reviewed-by: Avri Altman &lt;avri.altman@wdc.com&gt;
Message-ID: &lt;20241125132311.23939-1-ulf.hansson@linaro.org&gt;
</content>
</entry>
<entry>
<title>mmc: core: Support UHS-II card control and access</title>
<updated>2024-10-24T12:22:24Z</updated>
<author>
<name>Victor Shih</name>
<email>victor.shih@genesyslogic.com.tw</email>
</author>
<published>2024-10-18T10:53:18Z</published>
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<id>urn:sha1:9a9f7e13952b2638bc57bc9b34e6bdd106509836</id>
<content type='text'>
Embed UHS-II access/control functionality into the MMC request
processing flow.

Signed-off-by: Jason Lai &lt;jason.lai@genesyslogic.com.tw&gt;
Signed-off-by: Victor Shih &lt;victor.shih@genesyslogic.com.tw&gt;
Message-ID: &lt;20241018105333.4569-2-victorshihgli@gmail.com&gt;
[Ulf: A couple of cleanups and fixed sd_uhs2_power_off()]
Signed-off-by: Ulf Hansson &lt;ulf.hansson@linaro.org&gt;
</content>
</entry>
<entry>
<title>mmc: core: Add definitions for SD UHS-II cards</title>
<updated>2024-10-14T10:40:10Z</updated>
<author>
<name>Victor Shih</name>
<email>victor.shih@genesyslogic.com.tw</email>
</author>
<published>2024-09-13T10:28:19Z</published>
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<id>urn:sha1:a9a75f9dc23c1562dcb261c0a8f3d6fc70d246cd</id>
<content type='text'>
Add UHS-II specific data structures for commands and defines for
registers, as described in Part 1 UHS-II Addendum Version 1.01.

UHS-II related definitions are listed below:
  1. UHS-II card capability: sd_uhs2_caps{}
  2. UHS-II configuration: sd_uhs2_config{}
  3. UHS-II register I/O address and register field definitions: sd_uhs2.h

Signed-off-by: Jason Lai &lt;jason.lai@genesyslogic.com.tw&gt;
Signed-off-by: Victor Shih &lt;victor.shih@genesyslogic.com.tw&gt;
Link: https://lore.kernel.org/r/20240913102836.6144-6-victorshihgli@gmail.com
Signed-off-by: Ulf Hansson &lt;ulf.hansson@linaro.org&gt;
</content>
</entry>
<entry>
<title>mmc: core: Extend support for mmc regulators with a vqmmc2</title>
<updated>2024-10-14T10:40:10Z</updated>
<author>
<name>Ulf Hansson</name>
<email>ulf.hansson@linaro.org</email>
</author>
<published>2024-09-13T10:28:18Z</published>
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<id>urn:sha1:a56ffd3a83ed2e10e0d9e0b199547bfa0d206aac</id>
<content type='text'>
To allow an additional external regulator to be controlled by an mmc host
driver, let's add support for a vqmmc2 regulator to the mmc core.

For an SD UHS-II interface the vqmmc2 regulator may correspond to the so
called vdd2 supply, as described by the SD spec. Initially, only 1.8V is
needed, hence limit the new helper function, mmc_regulator_set_vqmmc2() to
this too.

Note that, to allow for flexibility mmc host drivers need to manage the
enable/disable of the vqmmc2 regulator themselves, while the regulator is
looked up through the common mmc_regulator_get_supply().

Signed-off-by: Ulf Hansson &lt;ulf.hansson@linaro.org&gt;
Link: https://lore.kernel.org/r/20240913102836.6144-5-victorshihgli@gmail.com
</content>
</entry>
<entry>
<title>mmc: core: Announce successful insertion of an SD UHS-II card</title>
<updated>2024-10-14T10:40:10Z</updated>
<author>
<name>Ulf Hansson</name>
<email>ulf.hansson@linaro.org</email>
</author>
<published>2024-09-13T10:28:17Z</published>
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<id>urn:sha1:153196d550c747367bdbec5cd545a572c5310451</id>
<content type='text'>
To inform the users about SD UHS-II cards, let's extend the print at card
insertion with a "UHS-II" substring. Within this change, it seems
reasonable to convert from using "ultra high speed" into "UHS-I speed", for
the UHS-I type, as it should makes it more clear.

Note that, the new print for UHS-II cards doesn't include the actual
selected speed mode. Instead, this is going to be added from subsequent
change.

Signed-off-by: Ulf Hansson &lt;ulf.hansson@linaro.org&gt;
Link: https://lore.kernel.org/r/20240913102836.6144-4-victorshihgli@gmail.com
</content>
</entry>
<entry>
<title>mmc: core: Prepare to support SD UHS-II cards</title>
<updated>2024-10-14T10:40:10Z</updated>
<author>
<name>Ulf Hansson</name>
<email>ulf.hansson@linaro.org</email>
</author>
<published>2024-09-13T10:28:16Z</published>
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<id>urn:sha1:79daeb241db7901e4bd53cce9ab046f376a63a4c</id>
<content type='text'>
The SD UHS-II interface was introduced to the SD spec v4.00 several years
ago. The interface is fundamentally different from an electrical and a
protocol point of view, comparing to the legacy SD interface.

However, the legacy SD protocol is supported through a specific transport
layer (SD-TRAN) defined in the UHS-II addendum of the spec. This allows the
SD card to be managed in a very similar way as a legacy SD card, hence a
lot of code can be re-used to support these new types of cards through the
mmc subsystem.

Moreover, an SD card that supports the UHS-II interface shall also be
backwards compatible with the legacy SD interface, which allows a UHS-II
card to be inserted into a legacy slot. As a matter of fact, this is
already supported by mmc subsystem as of today.

To prepare to add support for UHS-II, this change puts the basic foundation
in the mmc core in place, allowing it to be more easily reviewed before
subsequent changes implements the actual support.

Basically, the approach here adds a new UHS-II bus_ops type and adds a
separate initialization path for the UHS-II card. The intent is to avoid us
from sprinkling the legacy initialization path, but also to simplify
implementation of the UHS-II specific bits.

At this point, there is only one new host ops added to manage the various
ios settings needed for UHS-II. Additional host ops that are needed, are
being added from subsequent changes.

Signed-off-by: Ulf Hansson &lt;ulf.hansson@linaro.org&gt;
Link: https://lore.kernel.org/r/20240913102836.6144-3-victorshihgli@gmail.com
</content>
</entry>
<entry>
<title>mmc: core: Add open-ended Ext memory addressing</title>
<updated>2024-10-14T10:29:01Z</updated>
<author>
<name>Avri Altman</name>
<email>avri.altman@wdc.com</email>
</author>
<published>2024-10-06T05:11:42Z</published>
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<id>urn:sha1:403a0293f1c230524e0185b31f69c02a6aed12c7</id>
<content type='text'>
For open-ended read/write - just send CMD22 before issuing the command.

Reviewed-by: Adrian Hunter &lt;adrian.hunter@intel.com&gt;
Signed-off-by: Avri Altman &lt;avri.altman@wdc.com&gt;
Link: https://lore.kernel.org/r/20241006051148.160278-5-avri.altman@wdc.com
Signed-off-by: Ulf Hansson &lt;ulf.hansson@linaro.org&gt;
</content>
</entry>
<entry>
<title>mmc: sd: Add Extension memory addressing</title>
<updated>2024-10-14T10:29:01Z</updated>
<author>
<name>Avri Altman</name>
<email>avri.altman@wdc.com</email>
</author>
<published>2024-10-06T05:11:40Z</published>
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<id>urn:sha1:375b535941bea65b37451f0fd398e28bf4f3bdc3</id>
<content type='text'>
SDUC memory addressing spans beyond 2TB and up to 128TB.  Therefore, 38
bits are required to access the entire memory space of all sectors.
Those extra 6 bits are to be carried by CMD22 prior of sending
read/write/erase commands: CMD17, CMD18, CMD24, CMD25, CMD32, and CMD33.

CMD22 will carry the higher order 6 bits, and must precedes any of the
above commands even if it targets sector &lt; 2TB.

No error related to address or length is indicated in CMD22 but rather
in the read/write command itself.

Tested-by: Ricky WU &lt;ricky_wu@realtek.com&gt;
Reviewed-by: Adrian Hunter &lt;adrian.hunter@intel.com&gt;
Signed-off-by: Avri Altman &lt;avri.altman@wdc.com&gt;
Link: https://lore.kernel.org/r/20241006051148.160278-3-avri.altman@wdc.com
Signed-off-by: Ulf Hansson &lt;ulf.hansson@linaro.org&gt;
</content>
</entry>
</feed>
