<feed xmlns='http://www.w3.org/2005/Atom'>
<title>kernel/include/linux/mlx5/port.h, branch linux-5.10.y</title>
<subtitle>Hosts the 0x221E linux distro kernel.</subtitle>
<id>https://universe.0xinfinity.dev/distro/kernel/atom?h=linux-5.10.y</id>
<link rel='self' href='https://universe.0xinfinity.dev/distro/kernel/atom?h=linux-5.10.y'/>
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<updated>2020-09-17T16:33:03Z</updated>
<entry>
<title>RDMA/mlx5: Delete duplicated mlx5_ptys_width enum</title>
<updated>2020-09-17T16:33:03Z</updated>
<author>
<name>Aharon Landau</name>
<email>aharonl@mellanox.com</email>
</author>
<published>2020-09-17T09:02:22Z</published>
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<id>urn:sha1:e27014bdb47eb435f78573685f4196c07329f1f7</id>
<content type='text'>
Combine two same enums to avoid duplication.

Signed-off-by: Aharon Landau &lt;aharonl@mellanox.com&gt;
Reviewed-by: Michael Guralnik &lt;michaelgur@nvidia.com&gt;
Signed-off-by: Leon Romanovsky &lt;leonro@nvidia.com&gt;
</content>
</entry>
<entry>
<title>net/mlx5: Refactor query port speed functions</title>
<updated>2020-09-17T16:33:02Z</updated>
<author>
<name>Aharon Landau</name>
<email>aharonl@mellanox.com</email>
</author>
<published>2020-09-17T09:02:21Z</published>
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<id>urn:sha1:639bf4415cadff4c18e13aa5cb0dba2d443e3aa7</id>
<content type='text'>
The functions mlx5_query_port_link_width_oper and
mlx5_query_port_ib_proto_oper are always called together, so combine them
to a new function called mlx5_query_port_oper to avoid duplication.

And while the mlx5i_get_port_settings is the same as
mlx5_query_port_oper therefore let's remove it.

According to the IB spec link_width_oper and ib_proto_oper should be u16
and not as written u8, so perform casting as a preparation to cross-RDMA
patch which will fix that type for all drivers in the RDMA subsystem.

Fixes: ada68c31ba9c ("net/mlx5: Introduce a new header file for physical port functions")
Signed-off-by: Aharon Landau &lt;aharonl@mellanox.com&gt;
Reviewed-by: Michael Guralnik &lt;michaelgur@nvidia.com&gt;
Signed-off-by: Leon Romanovsky &lt;leonro@nvidia.com&gt;
</content>
</entry>
<entry>
<title>net/mlx5: Added support for 100Gbps per lane link modes</title>
<updated>2020-07-08T22:30:42Z</updated>
<author>
<name>Meir Lichtinger</name>
<email>meirl@mellanox.com</email>
</author>
<published>2020-07-07T03:42:33Z</published>
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<id>urn:sha1:12fdafb817c6cde87a4fa0e674e66b0226a0889d</id>
<content type='text'>
This patch exposes new link modes using 100Gbps per lane, including 100G,
200G and 400G modes.

Signed-off-by: Meir Lichtinger &lt;meirl@mellanox.com&gt;
Reviewed-by: Aya Levin &lt;ayal@mellanox.com&gt;
Signed-off-by: Saeed Mahameed &lt;saeedm@mellanox.com&gt;
Signed-off-by: David S. Miller &lt;davem@davemloft.net&gt;
</content>
</entry>
<entry>
<title>net/mlx5e: ethtool, Add support for EEPROM high pages query</title>
<updated>2019-05-01T21:39:16Z</updated>
<author>
<name>Erez Alfasi</name>
<email>ereza@mellanox.com</email>
</author>
<published>2019-03-21T13:02:13Z</published>
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<id>urn:sha1:a708fb7b1f8dcc7a8ed949839958cd5d812dd939</id>
<content type='text'>
Add the support to read additional EEPROM information from high pages.
Information for modules such as SFF-8436 and SFF-8636:
 1) Application select table
 2) User writable EEPROM
 3) Thresholds and alarms

Signed-off-by: Erez Alfasi &lt;ereza@mellanox.com&gt;
Signed-off-by: Saeed Mahameed &lt;saeedm@mellanox.com&gt;
</content>
</entry>
<entry>
<title>net/mlx5e: Fix GRE key by controlling port tunnel entropy calculation</title>
<updated>2019-02-22T21:38:23Z</updated>
<author>
<name>Eli Britstein</name>
<email>elibr@mellanox.com</email>
</author>
<published>2019-01-14T08:07:44Z</published>
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<id>urn:sha1:97417f6182f80a80c9b4443f282ef707be74dade</id>
<content type='text'>
Flow entropy is calculated on the inner packet headers and used for
flow distribution in processing, routing etc. For GRE-type
encapsulations the entropy value is placed in the eight LSB of the key
field in the GRE header as defined in NVGRE RFC 7637. For UDP based
encapsulations the entropy value is placed in the source port of the
UDP header.
The hardware may support entropy calculation specifically for GRE and
for all tunneling protocols. With commit df2ef3bff193 ("net/mlx5e: Add
GRE protocol offloading") GRE is offloaded, but the hardware is
configured by default to calculate flow entropy so packets transmitted
on the wire have a wrong key. To support UDP based tunnels (i.e VXLAN),
GRE (i.e. no flow entropy) and NVGRE (i.e. with flow entropy) the
hardware behaviour must be controlled by the driver.

Ensure port entropy calculation is enabled for offloaded VXLAN tunnels
and disable port entropy calculation in the presence of offloaded GRE
tunnels by monitoring the presence of entropy enabling tunnels (i.e
VXLAN) and entropy disabing tunnels (i.e GRE).

Fixes: df2ef3bff193 ("net/mlx5e: Add GRE protocol offloading")
Signed-off-by: Eli Britstein &lt;elibr@mellanox.com&gt;
Reviewed-by: Oz Shlomo &lt;ozsh@mellanox.com&gt;
Reviewed-by: Roi Dayan &lt;roid@mellanox.com&gt;
Signed-off-by: Saeed Mahameed &lt;saeedm@mellanox.com&gt;
</content>
</entry>
<entry>
<title>net/mlx5: Add support to ext_* fields introduced in Port Type and Speed register</title>
<updated>2019-02-14T20:14:42Z</updated>
<author>
<name>Aya Levin</name>
<email>ayal@mellanox.com</email>
</author>
<published>2019-02-13T06:55:45Z</published>
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<id>urn:sha1:a08b4ed1373dc59e3e15029bc6f135ba0f53c9a7</id>
<content type='text'>
This patch exposes new link modes (including 50Gbps per lane), and ext_*
fields which describes the new link modes in Port Type and Speed
register (PTYS).
Access functions, translation functions (speed &lt;-&gt; HW bits) and
link max speed function were modified.

Signed-off-by: Aya Levin &lt;ayal@mellanox.com&gt;
Reviewed-by: Eran Ben Elisha &lt;eranbe@mellanox.com&gt;
Signed-off-by: Saeed Mahameed &lt;saeedm@mellanox.com&gt;
</content>
</entry>
<entry>
<title>net/mlx5: Refactor queries to speed fields in Port Type and Speed register</title>
<updated>2019-02-14T20:14:42Z</updated>
<author>
<name>Aya Levin</name>
<email>ayal@mellanox.com</email>
</author>
<published>2019-02-13T06:55:43Z</published>
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<id>urn:sha1:bc4e12ffefdd886057eabe38135515690d0756a6</id>
<content type='text'>
This patch fascicles queries to speed related fields in Port Type and
Speed register (PTYS) into a single API. I addition, this patch
refactors functions which serves only Ethernet driver: remove the
protocol type as an input parameter, move code from 'core' directory
into 'en' directory and add 'eth' prefix to the function's name. The
patch also encapsulates functions that are not used outside the Ethernet
driver removes redundant include files.

Signed-off-by: Aya Levin &lt;ayal@mellanox.com&gt;
Reviewed-by: Eran Ben Elisha &lt;eranbe@mellanox.com&gt;
Signed-off-by: Saeed Mahameed &lt;saeedm@mellanox.com&gt;
</content>
</entry>
<entry>
<title>net/mlx5: Device events, Use async events chain</title>
<updated>2018-11-26T21:39:34Z</updated>
<author>
<name>Saeed Mahameed</name>
<email>saeedm@mellanox.com</email>
</author>
<published>2018-11-20T22:12:27Z</published>
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<id>urn:sha1:69c1280b1f3b9123bc5154b2062507abcc14c3ef</id>
<content type='text'>
Move all the generic async events handling into new specific events
handling file events.c to keep eq.c file clean from concrete event logic
handling.

Use new API to register for NOTIFY_ANY to handle generic events and
dispatch allowed events to mlx5_core consumers (mlx5_ib and mlx5e)

Signed-off-by: Saeed Mahameed &lt;saeedm@mellanox.com&gt;
</content>
</entry>
<entry>
<title>net/mlx5e: PFC stall prevention support</title>
<updated>2018-03-26T20:46:46Z</updated>
<author>
<name>Inbar Karmy</name>
<email>inbark@mellanox.com</email>
</author>
<published>2017-11-20T16:06:20Z</published>
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<id>urn:sha1:2afa609f5c970185a8cae73f6a4caadf97fbea54</id>
<content type='text'>
Implement set/get functions to configure PFC stall prevention
timeout by tunables api through ethtool.
By default the stall prevention timeout is configured to 8 sec.
Timeout range is: 80-8000 msec.

Enabling stall prevention with the auto timeout will set
the timeout to 100 msec.

Signed-off-by: Inbar Karmy &lt;inbark@mellanox.com&gt;
Signed-off-by: Saeed Mahameed &lt;saeedm@mellanox.com&gt;
</content>
</entry>
<entry>
<title>net/mlx5: QPTS and QPDPM register firmware command support</title>
<updated>2017-11-05T04:26:21Z</updated>
<author>
<name>Huy Nguyen</name>
<email>huyn@mellanox.com</email>
</author>
<published>2017-07-18T21:08:46Z</published>
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<id>urn:sha1:415a64aa8dc6b4fc478609c549ca652d95a12f13</id>
<content type='text'>
The QPTS register allows changing the priority trust state between pcp and
dscp. Add support to get/set trust state from device. When the port is
in pcp/dscp trust state, packet is routed by hardware to matching priority
based on its pcp/dscp value respectively.

The QPDPM register allow channing the dscp to priority mapping. Add support
to get/set dscp to priority mapping from device.
Note that to change a dscp mapping, the "e" bit of this dscp structure
must be set in the QPDPM firmware command.

Signed-off-by: Huy Nguyen &lt;huyn@mellanox.com&gt;
Reviewed-by: Parav Pandit &lt;parav@mellanox.com&gt;
Reviewed-by: Or Gerlitz &lt;ogerlitz@mellanox.com&gt;
Signed-off-by: Saeed Mahameed &lt;saeedm@mellanox.com&gt;
</content>
</entry>
</feed>
