<feed xmlns='http://www.w3.org/2005/Atom'>
<title>kernel/include/linux/mlx5/mlx5_ifc.h, branch linux-5.2.y</title>
<subtitle>Hosts the 0x221E linux distro kernel.</subtitle>
<id>https://universe.0xinfinity.dev/distro/kernel/atom?h=linux-5.2.y</id>
<link rel='self' href='https://universe.0xinfinity.dev/distro/kernel/atom?h=linux-5.2.y'/>
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<updated>2019-08-09T15:51:46Z</updated>
<entry>
<title>net/mlx5: Fix modify_cq_in alignment</title>
<updated>2019-08-09T15:51:46Z</updated>
<author>
<name>Edward Srouji</name>
<email>edwards@mellanox.com</email>
</author>
<published>2019-07-23T07:12:55Z</published>
<link rel='alternate' type='text/html' href='https://universe.0xinfinity.dev/distro/kernel/commit/?id=901092bf0afb955bb667eaf9cf8dbb5fbb95c51a'/>
<id>urn:sha1:901092bf0afb955bb667eaf9cf8dbb5fbb95c51a</id>
<content type='text'>
[ Upstream commit 7a32f2962c56d9d8a836b4469855caeee8766bd4 ]

Fix modify_cq_in alignment to match the device specification.
After this fix the 'cq_umem_valid' field will be in the right offset.

Cc: &lt;stable@vger.kernel.org&gt; # 4.19
Fixes: bd37197554eb ("net/mlx5: Update mlx5_ifc with DEVX UID bits")
Signed-off-by: Edward Srouji &lt;edwards@mellanox.com&gt;
Reviewed-by: Yishai Hadas &lt;yishaih@mellanox.com&gt;
Signed-off-by: Leon Romanovsky &lt;leonro@mellanox.com&gt;
Signed-off-by: Saeed Mahameed &lt;saeedm@mellanox.com&gt;
Signed-off-by: Greg Kroah-Hartman &lt;gregkh@linuxfoundation.org&gt;
</content>
</entry>
<entry>
<title>net/mlx5e: Rx, Fix checksum calculation for new hardware</title>
<updated>2019-07-28T06:27:19Z</updated>
<author>
<name>Saeed Mahameed</name>
<email>saeedm@mellanox.com</email>
</author>
<published>2019-05-03T20:14:59Z</published>
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<id>urn:sha1:9f71542e21bf80444302c8e28c2fd3cd51038af2</id>
<content type='text'>
[ Upstream commit db849faa9bef993a1379dc510623f750a72fa7ce ]

CQE checksum full mode in new HW, provides a full checksum of rx frame.
Covering bytes starting from eth protocol up to last byte in the received
frame (frame_size - ETH_HLEN), as expected by the stack.

Fixing up skb-&gt;csum by the driver is not required in such case. This fix
is to avoid wrong checksum calculation in drivers which already support
the new hardware with the new checksum mode.

Fixes: 85327a9c4150 ("net/mlx5: Update the list of the PCI supported devices")
Signed-off-by: Saeed Mahameed &lt;saeedm@mellanox.com&gt;
Signed-off-by: Greg Kroah-Hartman &lt;gregkh@linuxfoundation.org&gt;
</content>
</entry>
<entry>
<title>Merge tag 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/rdma/rdma</title>
<updated>2019-05-15T03:56:31Z</updated>
<author>
<name>Linus Torvalds</name>
<email>torvalds@linux-foundation.org</email>
</author>
<published>2019-05-15T03:56:31Z</published>
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<id>urn:sha1:5ac94332248ee017964ba368cdda4ce647e3aba7</id>
<content type='text'>
Pull more rdma updates from Jason Gunthorpe:
 "This is being sent to get a fix for the gcc 9.1 build warnings, and
  I've also pulled in some bug fix patches that were posted in the last
  two weeks.

   - Avoid the gcc 9.1 warning about overflowing a union member

   - Fix the wrong callback type for a single response netlink to doit

   - Bug fixes from more usage of the mlx5 devx interface"

* tag 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/rdma/rdma:
  net/mlx5: Set completion EQs as shared resources
  IB/mlx5: Verify DEVX general object type correctly
  RDMA/core: Change system parameters callback from dumpit to doit
  RDMA: Directly cast the sockaddr union to sockaddr
</content>
</entry>
<entry>
<title>net/mlx5: Set completion EQs as shared resources</title>
<updated>2019-05-14T13:22:09Z</updated>
<author>
<name>Yishai Hadas</name>
<email>yishaih@mellanox.com</email>
</author>
<published>2019-05-14T11:44:12Z</published>
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<id>urn:sha1:c191f93454bcc92810b9c8cdb895a452a57948c2</id>
<content type='text'>
Mark completion EQs as shared resources so that they can be used by CQs
with uid != 0.

Fixes: 7efce3691d33 ("IB/mlx5: Add obj create and destroy functionality")
Signed-off-by: Yishai Hadas &lt;yishaih@mellanox.com&gt;
Signed-off-by: Saeed Mahameed &lt;saeedm@mellanox.com&gt;
Signed-off-by: Leon Romanovsky &lt;leonro@mellanox.com&gt;
Signed-off-by: Jason Gunthorpe &lt;jgg@mellanox.com&gt;
</content>
</entry>
<entry>
<title>Merge branch 'mlx5-next' of git://git.kernel.org/pub/scm/linux/kernel/git/mellanox/linux</title>
<updated>2019-05-01T20:57:48Z</updated>
<author>
<name>Saeed Mahameed</name>
<email>saeedm@mellanox.com</email>
</author>
<published>2019-05-01T20:57:17Z</published>
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<id>urn:sha1:c515e70d675421240ff6628a1831a56e4ea0e82c</id>
<content type='text'>
This merge commit includes some misc shared code updates from mlx5-next branch needed
for net-next.

1) From Aya: Enable general events on all physical link types and
   restrict general event handling of subtype DELAY_DROP_TIMEOUT in mlx5 rdma
   driver to ethernet links only as it was intended.

2) From Eli: Introduce low level bits for prio tag mode

3) From Maor: Low level steering updates to support RDMA RX flow
   steering and enables RoCE loopback traffic when switchdev is enabled.

4) From Vu and Parav: Two small mlx5 core cleanups

5) From Yevgeny add HW definitions of geneve offloads

Signed-off-by: Saeed Mahameed &lt;saeedm@mellanox.com&gt;
</content>
</entry>
<entry>
<title>net/mlx5: Fix broken hca cap offset</title>
<updated>2019-05-01T20:38:47Z</updated>
<author>
<name>Saeed Mahameed</name>
<email>saeedm@mellanox.com</email>
</author>
<published>2019-05-01T03:21:05Z</published>
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<id>urn:sha1:91a40a48d52d13fbde3239d5839335cabd9a4eae</id>
<content type='text'>
The cited commit broke the offsets of hca cap struct, fix it.
While at it, cleanup a white space introduced by the same commit.

Fixes: b169e64a2444 ("net/mlx5: Geneve, Add flow table capabilities for Geneve decap with TLV options")
Reported-by: Qian Cai &lt;cai@lca.pw&gt;
Cc: Yevgeny Kliteynik &lt;kliteyn@mellanox.com&gt;
Signed-off-by: Saeed Mahameed &lt;saeedm@mellanox.com&gt;
</content>
</entry>
<entry>
<title>net/mlx5: Geneve, Add flow table capabilities for Geneve decap with TLV options</title>
<updated>2019-04-29T23:55:38Z</updated>
<author>
<name>Yevgeny Kliteynik</name>
<email>kliteyn@mellanox.com</email>
</author>
<published>2019-04-29T18:14:20Z</published>
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<id>urn:sha1:b169e64a24442e02cafee1586f17fcb713fe65a6</id>
<content type='text'>
Introduce specification for Geneve decap flow with encapsulation options
and allow creation of rules that are matching on Geneve TLV options.

Reviewed-by: Oz Shlomo &lt;ozsh@mellanox.com&gt;
Signed-off-by: Yevgeny Kliteynik &lt;kliteyn@mellanox.com&gt;
Signed-off-by: Saeed Mahameed &lt;saeedm@mellanox.com&gt;
</content>
</entry>
<entry>
<title>net/mlx5: Geneve, Add basic Geneve encap/decap flow table capabilities</title>
<updated>2019-04-29T23:55:38Z</updated>
<author>
<name>Yevgeny Kliteynik</name>
<email>kliteyn@mellanox.com</email>
</author>
<published>2019-04-29T18:14:18Z</published>
<link rel='alternate' type='text/html' href='https://universe.0xinfinity.dev/distro/kernel/commit/?id=75d90e7def8e20b57c1de9e2b672c3bf9249da83'/>
<id>urn:sha1:75d90e7def8e20b57c1de9e2b672c3bf9249da83</id>
<content type='text'>
Introduce support for Geneve flow specification and allow
the creation of rules that are matching on basic Geneve
protocol fields: VNI, OAM bit, protocol type, options length.

Reviewed-by: Oz Shlomo &lt;ozsh@mellanox.com&gt;
Signed-off-by: Yevgeny Kliteynik &lt;kliteyn@mellanox.com&gt;
Signed-off-by: Saeed Mahameed &lt;saeedm@mellanox.com&gt;
</content>
</entry>
<entry>
<title>net/mlx5: Add new miss flow table action</title>
<updated>2019-04-29T23:55:05Z</updated>
<author>
<name>Maor Gottlieb</name>
<email>maorg@mellanox.com</email>
</author>
<published>2019-04-29T18:14:14Z</published>
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<id>urn:sha1:f6f7d6b5bd818cc84eebb55ba6bcba38cfd3b385</id>
<content type='text'>
Flow table supports three types of miss action:
1. Default miss action - go to default miss table according to table.
2. Go to specific table.
3. Switch domain - go to the root table of an alternative steering
   table domain.

New table miss action was added - switch_domain.
The next domain for RDMA_RX namespace is the NIC RX domain.

Signed-off-by: Maor Gottlieb &lt;maorg@mellanox.com&gt;
Reviewed-by: Mark Bloch &lt;markb@mellanox.com&gt;
Signed-off-by: Saeed Mahameed &lt;saeedm@mellanox.com&gt;
</content>
</entry>
<entry>
<title>net/mlx5: Add support in RDMA RX steering</title>
<updated>2019-04-29T23:55:05Z</updated>
<author>
<name>Maor Gottlieb</name>
<email>maorg@mellanox.com</email>
</author>
<published>2019-04-29T18:14:12Z</published>
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<id>urn:sha1:d83eb50e29de36ddc819863ab7b9d2da58bccbd0</id>
<content type='text'>
Add new flow steering namespace - MLX5_FLOW_NAMESPACE_RDMA_RX.
Flow steering rules in this namespace are used to filter
RDMA traffic.

Signed-off-by: Maor Gottlieb &lt;maorg@mellanox.com&gt;
Reviewed-by: Mark Bloch &lt;markb@mellanox.com&gt;
Signed-off-by: Saeed Mahameed &lt;saeedm@mellanox.com&gt;
</content>
</entry>
</feed>
