<feed xmlns='http://www.w3.org/2005/Atom'>
<title>kernel/include/linux/mlx5/cq.h, branch linux-5.11.y</title>
<subtitle>Hosts the 0x221E linux distro kernel.</subtitle>
<id>https://universe.0xinfinity.dev/distro/kernel/atom?h=linux-5.11.y</id>
<link rel='self' href='https://universe.0xinfinity.dev/distro/kernel/atom?h=linux-5.11.y'/>
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<updated>2020-06-27T20:50:46Z</updated>
<entry>
<title>net/mlx5: Avoid RDMA file inclusion in core driver</title>
<updated>2020-06-27T20:50:46Z</updated>
<author>
<name>Parav Pandit</name>
<email>parav@mellanox.com</email>
</author>
<published>2020-06-26T05:59:41Z</published>
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<id>urn:sha1:9205d7b1c1cffa827c23bdbf35e04c7cbe1e1f10</id>
<content type='text'>
mlx5 cq.h does not depend on RDMA verbs.
Remove RDMA verbs file inclusion.

Signed-off-by: Parav Pandit &lt;parav@mellanox.com&gt;
Signed-off-by: Saeed Mahameed &lt;saeedm@mellanox.com&gt;
</content>
</entry>
<entry>
<title>net/mlx5: Update cq.c to new cmd interface</title>
<updated>2020-04-23T18:42:03Z</updated>
<author>
<name>Leon Romanovsky</name>
<email>leonro@mellanox.com</email>
</author>
<published>2020-04-09T08:39:14Z</published>
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<id>urn:sha1:d1f620500cde5c72c7b96a19474733c4c6c67f38</id>
<content type='text'>
Do mass update of cq.c to reuse newly introduced
mlx5_cmd_exec_in*() interfaces.

Reviewed-by: Moshe Shemesh &lt;moshe@mellanox.com&gt;
Signed-off-by: Leon Romanovsky &lt;leonro@mellanox.com&gt;
</content>
</entry>
<entry>
<title>net/mlx5: Report EQE data upon CQ completion</title>
<updated>2019-07-03T18:00:20Z</updated>
<author>
<name>Yishai Hadas</name>
<email>yishaih@mellanox.com</email>
</author>
<published>2019-06-30T16:23:27Z</published>
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<id>urn:sha1:4e0e2ea1886afe8c001971ff767f6670312a9b04</id>
<content type='text'>
Report EQE data upon CQ completion to let upper layers use this data.

Signed-off-by: Yishai Hadas &lt;yishaih@mellanox.com&gt;
Acked-by: Saeed Mahameed &lt;saeedm@mellanox.com&gt;
Signed-off-by: Leon Romanovsky &lt;leonro@mellanox.com&gt;
</content>
</entry>
<entry>
<title>net/mlx5: mlx5_core_create_cq() enhancements</title>
<updated>2019-07-03T17:59:32Z</updated>
<author>
<name>Yishai Hadas</name>
<email>yishaih@mellanox.com</email>
</author>
<published>2019-06-30T16:23:25Z</published>
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<id>urn:sha1:38164b771947be9baf06e78ffdfb650f8f3e908e</id>
<content type='text'>
Enhance mlx5_core_create_cq() to get the command out buffer from the
callers to let them use the output.

Signed-off-by: Yishai Hadas &lt;yishaih@mellanox.com&gt;
Acked-by: Saeed Mahameed &lt;saeedm@mellanox.com&gt;
Signed-off-by: Leon Romanovsky &lt;leonro@mellanox.com&gt;
</content>
</entry>
<entry>
<title>net/mlx5: Remove spinlock support from mlx5_write64</title>
<updated>2019-04-02T19:49:37Z</updated>
<author>
<name>Maxim Mikityanskiy</name>
<email>maximmi@mellanox.com</email>
</author>
<published>2019-03-29T22:37:52Z</published>
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<id>urn:sha1:bbf29f618e8c5bfd6efdad5fdc050a84bab795ab</id>
<content type='text'>
As there is no user of mlx5_write64 that passes a spinlock to
mlx5_write64, remove this functionality and simplify the function.

Signed-off-by: Maxim Mikityanskiy &lt;maximmi@mellanox.com&gt;
Reviewed-by: Eran Ben Elisha &lt;eranbe@mellanox.com&gt;
Signed-off-by: Saeed Mahameed &lt;saeedm@mellanox.com&gt;
</content>
</entry>
<entry>
<title>net/mlx5e: Use CQE padding for Ethernet CQs</title>
<updated>2018-12-11T22:52:20Z</updated>
<author>
<name>Daniel Jurgens</name>
<email>danielj@mellanox.com</email>
</author>
<published>2018-11-05T22:05:37Z</published>
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<id>urn:sha1:939de57d30344ce728b0de61be87984e75af420e</id>
<content type='text'>
Writing 64B CQEs to 128B cache lines results in a RMW operation. Padding
the CQEs to 128B if possible improves performance on 128B cache line
systems like PPC.

Testing on PPC showed up to a 24% improvement in small packet throughput
vs the default behavior, depending on the workload and system topology.

Signed-off-by: Daniel Jurgens &lt;danielj@mellanox.com&gt;
Reviewed-by: Tariq Toukan &lt;tariqt@mellanox.com&gt;
Signed-off-by: Saeed Mahameed &lt;saeedm@mellanox.com&gt;
</content>
</entry>
<entry>
<title>net/mlx5: EQ, Different EQ types</title>
<updated>2018-11-20T18:07:00Z</updated>
<author>
<name>Saeed Mahameed</name>
<email>saeedm@mellanox.com</email>
</author>
<published>2018-11-19T18:52:39Z</published>
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<id>urn:sha1:16d760839ceef510cf95cbfadc069c4473c7a277</id>
<content type='text'>
In mlx5 we have three types of usages for EQs,
1. Asynchronous EQs, used internally by mlx5 core for
 a. FW command completions
 b. FW page requests
 c. one EQ for all other Asynchronous events

2. Completion EQs, used for CQ completion (we create one per core)

3. *Special type of EQ (page fault) used for RDMA on demand paging
(ODP).

*The 3rd type shouldn't be special at least in mlx5 core, it is yet
another async events EQ with specific use case, it will be removed in
the next two patches, and will completely move its logic to mlx5_ib,
as it is rdma specific.

In this patch we remove use case (eq type) specific fields from
struct mlx5_eq into a new eq type specific structures.

struct mlx5_eq_async;
truct mlx5_eq_comp;
struct mlx5_eq_pagefault;

Separate between their type specific flows.

In the future we will allow users to create there own generic EQs.
for now we will allow only one for ODP in next patches.

We will introduce event listeners registration API for those who
want to receive mlx5 async events.
After that mlx5 eq handling will be clean from feature/user specific
handling.

Signed-off-by: Saeed Mahameed &lt;saeedm@mellanox.com&gt;
Reviewed-by: Leon Romanovsky &lt;leonro@mellanox.com&gt;
Reviewed-by: Tariq Toukan &lt;tariqt@mellanox.com&gt;
Signed-off-by: Leon Romanovsky &lt;leonro@mellanox.com&gt;
</content>
</entry>
<entry>
<title>net/mlx5: Set uid as part of CQ commands</title>
<updated>2018-09-25T06:52:35Z</updated>
<author>
<name>Yishai Hadas</name>
<email>yishaih@mellanox.com</email>
</author>
<published>2018-09-20T18:35:20Z</published>
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<id>urn:sha1:9ba481e2eb3b932ae5b6278342b256e4f92d2793</id>
<content type='text'>
Set uid as part of CQ commands so that the firmware can manage the CQ
object in a secured way.

The firmware should mark this CQ with the given uid so that it can
be used later on only by objects with the same uid.

Upon DEVX flows that use this CQ (e.g. create QP command), the
pointed CQ must have the same uid as of the issuer uid command.

When a command is issued with uid=0 it means that the issuer of the
command is trusted (i.e. kernel), in that case any pointed object
can be used regardless of its uid.

Signed-off-by: Yishai Hadas &lt;yishaih@mellanox.com&gt;
Signed-off-by: Leon Romanovsky &lt;leonro@mellanox.com&gt;
</content>
</entry>
<entry>
<title>mlx5: Move dump error CQE function out of mlx5_ib for code sharing</title>
<updated>2018-03-28T00:17:28Z</updated>
<author>
<name>Eran Ben Elisha</name>
<email>eranbe@mellanox.com</email>
</author>
<published>2017-12-31T10:55:26Z</published>
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<id>urn:sha1:1acae6b030164217b9c6a52245eade730057152b</id>
<content type='text'>
Move mlx5_ib dump error CQE implementation to mlx5 CQ header file in
order to use it in a downstream patch from mlx5e.

In addition, use print_hex_dump instead of manual dumping of the buffer.

Signed-off-by: Eran Ben Elisha &lt;eranbe@mellanox.com&gt;
Signed-off-by: Saeed Mahameed &lt;saeedm@mellanox.com&gt;
</content>
</entry>
<entry>
<title>net/mlx5: CQ hold/put API</title>
<updated>2018-02-15T08:30:01Z</updated>
<author>
<name>Saeed Mahameed</name>
<email>saeedm@mellanox.com</email>
</author>
<published>2018-02-01T11:32:00Z</published>
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<id>urn:sha1:f105b45bf77ced96e516e1cd771c41bb7e8c830b</id>
<content type='text'>
Now as the CQ table is per EQ, add an API to hold/put CQ to be used from
eq.c in downstream patch.

Signed-off-by: Saeed Mahameed &lt;saeedm@mellanox.com&gt;
Reviewed-by: Gal Pressman &lt;galp@mellanox.com&gt;
</content>
</entry>
</feed>
