<feed xmlns='http://www.w3.org/2005/Atom'>
<title>kernel/include/linux/mlx5/accel.h, branch linux-6.18.y</title>
<subtitle>Hosts the 0x221E linux distro kernel.</subtitle>
<id>https://universe.0xinfinity.dev/distro/kernel/atom?h=linux-6.18.y</id>
<link rel='self' href='https://universe.0xinfinity.dev/distro/kernel/atom?h=linux-6.18.y'/>
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<updated>2022-05-04T05:59:15Z</updated>
<entry>
<title>net/mlx5: Merge various control path IPsec headers into one file</title>
<updated>2022-05-04T05:59:15Z</updated>
<author>
<name>Leon Romanovsky</name>
<email>leonro@nvidia.com</email>
</author>
<published>2022-03-09T08:35:05Z</published>
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<id>urn:sha1:c6e3b421c7079af67201351c9faff62613e06f40</id>
<content type='text'>
The mlx5 IPsec code has logical separation between code that operates
with XFRM objects (ipsec.c), HW objects (ipsec_offload.c), flow steering
logic (ipsec_fs.c) and data path (ipsec_rxtx.c).

Such separation makes sense for C-files, but isn't needed at all for
H-files as they are included in batch anyway.

Reviewed-by: Raed Salem &lt;raeds@nvidia.com&gt;
Signed-off-by: Leon Romanovsky &lt;leonro@nvidia.com&gt;
Signed-off-by: Saeed Mahameed &lt;saeedm@nvidia.com&gt;
</content>
</entry>
<entry>
<title>net/mlx5: Remove useless validity check</title>
<updated>2022-05-04T05:59:15Z</updated>
<author>
<name>Leon Romanovsky</name>
<email>leonro@nvidia.com</email>
</author>
<published>2022-03-08T18:55:00Z</published>
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<id>urn:sha1:2ea36e2e4ad2b77bd5d45142a529b72eb5ca9156</id>
<content type='text'>
All callers build xfrm attributes with help of mlx5e_ipsec_build_accel_xfrm_attrs()
function that ensure validity of attributes. There is no need to recheck
them again.

Reviewed-by: Raed Salem &lt;raeds@nvidia.com&gt;
Signed-off-by: Leon Romanovsky &lt;leonro@nvidia.com&gt;
Signed-off-by: Saeed Mahameed &lt;saeedm@nvidia.com&gt;
</content>
</entry>
<entry>
<title>net/mlx5: Store IPsec ESN update work in XFRM state</title>
<updated>2022-05-04T05:59:15Z</updated>
<author>
<name>Leon Romanovsky</name>
<email>leonro@nvidia.com</email>
</author>
<published>2022-03-08T18:36:15Z</published>
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<id>urn:sha1:c674df973ad8af2074c834788e167332d81309fa</id>
<content type='text'>
mlx5 IPsec code updated ESN through workqueue with allocation calls
in the data path, which can be saved easily if the work is created
during XFRM state initialization routine.

The locking used later in the work didn't protect from anything because
change of HW context is possible during XFRM state add or delete only,
which can cancel work and make sure that it is not running.

Reviewed-by: Raed Salem &lt;raeds@nvidia.com&gt;
Signed-off-by: Leon Romanovsky &lt;leonro@nvidia.com&gt;
Signed-off-by: Saeed Mahameed &lt;saeedm@nvidia.com&gt;
</content>
</entry>
<entry>
<title>net/mlx5: Remove not-implemented IPsec capabilities</title>
<updated>2022-04-09T05:25:07Z</updated>
<author>
<name>Leon Romanovsky</name>
<email>leonro@nvidia.com</email>
</author>
<published>2022-04-06T08:25:52Z</published>
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<id>urn:sha1:2984287c4c19949d7eb451dcad0bd5c54a2a376f</id>
<content type='text'>
Clean a capabilities enum to remove not-implemented bits.

Link: https://lore.kernel.org/r/1044bb7b779107ff38e48e3f6553421104f3f819.1649232994.git.leonro@nvidia.com
Reviewed-by: Raed Salem &lt;raeds@nvidia.com&gt;
Signed-off-by: Leon Romanovsky &lt;leonro@nvidia.com&gt;
</content>
</entry>
<entry>
<title>net/mlx5: Remove not-needed IPsec config</title>
<updated>2022-04-09T05:25:07Z</updated>
<author>
<name>Leon Romanovsky</name>
<email>leonro@nvidia.com</email>
</author>
<published>2022-04-06T08:25:48Z</published>
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<id>urn:sha1:54deb0e77561973f4ca4515e18ab972c281eea1d</id>
<content type='text'>
In current code, the CONFIG_MLX5_IPSEC and CONFIG_MLX5_EN_IPSEC are
the same. So remove useless indirection.

Link: https://lore.kernel.org/r/fd14492cbc01a0d51a5bfedde02bcd2154123fde.1649232994.git.leonro@nvidia.com
Reviewed-by: Raed Salem &lt;raeds@nvidia.com&gt;
Signed-off-by: Leon Romanovsky &lt;leonro@nvidia.com&gt;
</content>
</entry>
<entry>
<title>net/mlx5: Unify device IPsec capabilities check</title>
<updated>2022-04-09T05:25:07Z</updated>
<author>
<name>Leon Romanovsky</name>
<email>leonro@nvidia.com</email>
</author>
<published>2022-04-06T08:25:46Z</published>
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<id>urn:sha1:2451da081a343e079d9f5a7b063fcdf0bc439aa8</id>
<content type='text'>
Merge two different function to one in order to provide coherent
picture if the device is IPsec capable or not.

Link: https://lore.kernel.org/r/8f10ea06ad19c6f651e9fb33921009658f01e1d5.1649232994.git.leonro@nvidia.com
Reviewed-by: Raed Salem &lt;raeds@nvidia.com&gt;
Signed-off-by: Leon Romanovsky &lt;leonro@nvidia.com&gt;
</content>
</entry>
<entry>
<title>RDMA/mlx5: Drop crypto flow steering API</title>
<updated>2022-04-09T05:25:06Z</updated>
<author>
<name>Leon Romanovsky</name>
<email>leonro@nvidia.com</email>
</author>
<published>2022-04-06T08:25:42Z</published>
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<id>urn:sha1:de8bdb476908e64805df4bfbad20618cbb1f9ffa</id>
<content type='text'>
The mlx5 flow steering crypto API was intended to be used in FPGA
devices, which is not supported for years already. The removal of
mlx5 crypto FPGA code together with inability to configure encryption
keys makes the low steering API completely unusable.

So delete the code, so any ESP flow steering requests will fail with
not supported error, as it is happening now anyway as no device support
this type of API.

Link: https://lore.kernel.org/r/634a5face7734381463d809bfb89850f6998deac.1649232994.git.leonro@nvidia.com
Reviewed-by: Raed Salem &lt;raeds@nvidia.com&gt;
Signed-off-by: Leon Romanovsky &lt;leonro@nvidia.com&gt;
</content>
</entry>
<entry>
<title>net/mlx5: Accel, Add core IPsec support for the Connect-X family</title>
<updated>2020-07-16T23:36:42Z</updated>
<author>
<name>Raed Salem</name>
<email>raeds@mellanox.com</email>
</author>
<published>2019-11-18T12:30:20Z</published>
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<id>urn:sha1:9a6ad1ad71fbc5a52617e016a3608d71b91f62e8</id>
<content type='text'>
This to set the base for downstream patches to support
the new IPsec implementation of the Connect-X family.

Following modifications made:
- Remove accel layer dependency from MLX5_FPGA_IPSEC.
- Introduce accel_ipsec_ops, each IPsec device will
  have to support these ops.

Signed-off-by: Raed Salem &lt;raeds@mellanox.com&gt;
Reviewed-by: Tariq Toukan &lt;tariqt@mellanox.com&gt;
Signed-off-by: Saeed Mahameed &lt;saeedm@mellanox.com&gt;
</content>
</entry>
<entry>
<title>net/mlx5: IPSec: Fix incorrect type for spi</title>
<updated>2020-05-30T04:20:22Z</updated>
<author>
<name>Saeed Mahameed</name>
<email>saeedm@mellanox.com</email>
</author>
<published>2020-05-29T07:47:12Z</published>
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<id>urn:sha1:44345c4c130ee3df9b9fbc366d59ab3ac707d7f8</id>
<content type='text'>
spi is __be32, fix that.

Fixes sparse warning:
drivers/net/ethernet/mellanox/mlx5/core/accel/ipsec.c:74:64
warning: incorrect type

Signed-off-by: Saeed Mahameed &lt;saeedm@mellanox.com&gt;
</content>
</entry>
<entry>
<title>net/mlx5: Refactor mlx5_accel_esp_create_hw_context parameter list</title>
<updated>2020-04-20T21:20:19Z</updated>
<author>
<name>Raed Salem</name>
<email>raeds@mellanox.com</email>
</author>
<published>2019-12-10T11:20:55Z</published>
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<id>urn:sha1:1dbd51d0a71a561056579e2d4f406e5ce5343af0</id>
<content type='text'>
Currently the FPGA IPsec is the only hw implementation of the IPsec
acceleration api, and so the mlx5_accel_esp_create_hw_context was
wrongly made to suit this HW api, among other in its parameter list
and some of its parameter endianness.

This implementation might not be suitable for different HW.

Refactor by group and pass all function arguments of
mlx5_accel_esp_create_hw_context in common mlx5_accel_esp_xfrm_attrs
struct field of mlx5_accel_esp_xfrm struct and correct the endianness
according to the HW being called.

Signed-off-by: Raed Salem &lt;raeds@mellanox.com&gt;
Reviewed-by: Boris Pismenny &lt;borisp@mellanox.com&gt;
Reviewed-by: Huy Nguyen &lt;huyn@mellanox.com&gt;
Signed-off-by: Saeed Mahameed &lt;saeedm@mellanox.com&gt;
</content>
</entry>
</feed>
