kernel/include/linux/mfd/stm32-timers.h, branch linux-6.18.y

mfd: stm32-timers: Add support for stm32mp25

2025-03-14T08:59:05Z

Add support for STM32MP25 SoC. Use newly introduced compatible, to handle new features. Identification and hardware configuration registers allow to read the timer version and capabilities (counter width, number of channels...). So, rework the probe to avoid touching ARR register by simply read the counter width when available. This may avoid messing with a possibly running timer. Also add useful bit fields to stm32-timers header file. Signed-off-by: Fabrice Gasnier Link: https://lore.kernel.org/r/20250110091922.980627-3-fabrice.gasnier@foss.st.com Signed-off-by: Lee Jones

mfd: stm32-timers: Drop unused TIM_DIER_CC_IE

2024-06-26T15:09:58Z

This macro is misleading as TIM_DIER_CC_IE(1) == TIM_DIER_CC2IE . The only user was updated to use TIM_DIER_CCxIE() instead which doesn't suffer from this mismatch, so TIM_DIER_CC_IE can be dropped. Signed-off-by: Uwe Kleine-König Link: https://lore.kernel.org/r/6c8fcc4ed159992a1dbb0796087e6ceb10c39c96.1718791090.git.u.kleine-koenig@baylibre.com Signed-off-by: Lee Jones

mfd: stm32-timers: Add some register definitions with a parameter

2024-06-26T15:09:52Z

There are some registers that belong together and are numbered from 1 to 4. Introduce a macro definition for these that takes the channel number as parameter and define the previously available constants using the new ones. This allows to simplify some users that up to now use constructs like TIM_CCER_CC1NE << (ch * 4) which is an ugly mix of using a predefined value and still knowing internal details about it. Note that there are several decrements by 1 involved. These are necessary because software guys start counting at 0 while the hardware designer started at 1 (and having TIM_CCER_CCxE(1) be TIM_CCER_CC2E isn't a sane option). The compiler is expected to optimize these out nicely. Signed-off-by: Uwe Kleine-König Link: https://lore.kernel.org/r/05df15f61dde81033407d3b4fcb67ee403ecc8db.1718791090.git.u.kleine-koenig@baylibre.com Signed-off-by: Lee Jones

mfd: stm32-timers: Unify alignment of register definition

2024-06-26T15:08:43Z

Use tabs consistently for indention and properly align register names, values and comments. This improves readability (at least for my eyes). Signed-off-by: Uwe Kleine-König Link: https://lore.kernel.org/r/da3b7f9af5794d7463aa62cbaa7251abf1af2018.1718791090.git.u.kleine-koenig@baylibre.com Signed-off-by: Lee Jones

counter: stm32-timer-cnt: add support for capture events

2024-04-02T17:10:34Z

Add support for capture events. Captured counter value for each channel can be retrieved through CCRx register. STM32 timers can have up to 4 capture channels (on input channel 1 to channel 4), hence need to check the number of channels before reading the capture data. The capture configuration is hard-coded to capture signals on both edges (non-inverted). Interrupts are used to report events independently for each channel. Reviewed-by: William Breathitt Gray Acked-by: Lee Jones Signed-off-by: Fabrice Gasnier Link: https://lore.kernel.org/r/20240307133306.383045-11-fabrice.gasnier@foss.st.com Signed-off-by: William Breathitt Gray

mfd: stm32-timers: Add support for interrupts

2023-11-01T10:02:12Z

There are two types of STM32 timers that may have: - a global interrupt line - 4 dedicated interrupt lines. Those interrupts are optional as defined in the dt-bindings. Enforce checks on either one, four or no interrupts are provided with their names. Optionally get them here, to be used by child devices. Signed-off-by: Fabrice Gasnier Link: https://lore.kernel.org/r/20230829134029.2402868-5-fabrice.gasnier@foss.st.com Signed-off-by: Lee Jones

pwm: stm32: Enforce settings for PWM capture

2023-04-06T14:35:01Z

The PWM capture assumes that the input selector is set to default input and that the slave mode is disabled. Force reset state for TISEL and SMCR registers to match this requirement. Note that slave mode disabling is not a pre-requisite by itself for capture mode, as hardware supports it for PWM capture. However, the current implementation of the driver does not allow slave mode for PWM capture. Setting slave mode for PWM capture results in wrong capture values. Signed-off-by: Olivier Moysan Acked-by: Lee Jones Acked-by: Uwe Kleine-König Signed-off-by: Thierry Reding

counter: stm32-timer-cnt: Provide defines for slave mode selection

2021-10-17T09:52:46Z

The STM32 timer permits configuration of the counter encoder mode via the slave mode control register (SMCR) slave mode selection (SMS) bits. This patch provides preprocessor defines for the supported encoder modes. Cc: Fabrice Gasnier Signed-off-by: William Breathitt Gray Reviewed-by: Fabrice Gasnier Link: https://lore.kernel.org/r/ad3d9cd7af580d586316d368f74964cbc394f981.1630031207.git.vilhelm.gray@gmail.com Signed-off-by: Jonathan Cameron

pwm: stm32: Remove clutter from ternary operator

2019-10-21T14:50:05Z

Remove usage of the ternary operator to assign values for register fields. Instead, parameterize the register and field offset macros and pass the index to them. This removes clutter and improves readability. Signed-off-by: Thierry Reding

mfd: stm32-timers: Fix pwm-stm32 linker issue with COMPILE_TEST

2018-06-04T06:14:17Z

This is seen when COMPILE_TEST=y and MFD_STM32_TIMERS=n. drivers/pwm/pwm-stm32.o: In function 'stm32_pwm_raw_capture': pwm-stm32.c:... undefined reference to 'stm32_timers_dma_burst_read' Fixes: 0c6609805b63 ("mfd: stm32-timers: Add support for DMAs") Signed-off-by: Fabrice Gasnier Reported-by: Randy Dunlap Tested-by: Randy Dunlap Signed-off-by: Lee Jones