<feed xmlns='http://www.w3.org/2005/Atom'>
<title>kernel/include/linux/mfd/lpc_ich.h, branch linux-3.17.y</title>
<subtitle>Hosts the 0x221E linux distro kernel.</subtitle>
<id>https://universe.0xinfinity.dev/distro/kernel/atom?h=linux-3.17.y</id>
<link rel='self' href='https://universe.0xinfinity.dev/distro/kernel/atom?h=linux-3.17.y'/>
<link rel='alternate' type='text/html' href='https://universe.0xinfinity.dev/distro/kernel/'/>
<updated>2014-03-19T09:00:02Z</updated>
<entry>
<title>mfd: lpc_ich: Add support for iTCO v3</title>
<updated>2014-03-19T09:00:02Z</updated>
<author>
<name>Peter Tyser</name>
<email>ptyser@xes-inc.com</email>
</author>
<published>2014-03-10T21:34:54Z</published>
<link rel='alternate' type='text/html' href='https://universe.0xinfinity.dev/distro/kernel/commit/?id=eb71d4dec4a5e010e34b9d7afdb5af41884c388e'/>
<id>urn:sha1:eb71d4dec4a5e010e34b9d7afdb5af41884c388e</id>
<content type='text'>
Some newer Atom CPUs, eg Avoton and Bay Trail, use slightly different
register layouts for the iTCO than the current v1 and v2 iTCO.
Differences from previous iTCO versions include:
- The ACPI space is enabled in the "ACPI base address" register instead
  of the "ACPI control register"

- The "no reboot" functionality is set in the "Power Management
  Configuration" register instead of the "General Control and Status"
  (GCS) register or PCI configuration space.

- The "ACPI Control Register" is not present on v3.  The "Power
  Management Configuration Base Address" register resides at the same
  address is Avoton/Bay Trail.

To differentiate these newer chipsets create a new v3 iTCO version and
update the MFD driver to support them.

Signed-off-by: Peter Tyser &lt;ptyser@xes-inc.com&gt;
Tested-by: Rajat Jain &lt;rajatjain@juniper.net&gt;
Reviewed-by: Guenter Roeck &lt;linux@roeck-us.net&gt;
Signed-off-by: Lee Jones &lt;lee.jones@linaro.org&gt;
</content>
</entry>
<entry>
<title>mfd: lpc_ich: Add support for Intel Avoton GPIOs</title>
<updated>2014-03-19T08:58:21Z</updated>
<author>
<name>Vincent Donnefort</name>
<email>vdonnefort@gmail.com</email>
</author>
<published>2014-02-14T14:01:54Z</published>
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<id>urn:sha1:facd9939403cb5769190054a600474399e776e3a</id>
<content type='text'>
Signed-off-by: Vincent Donnefort &lt;vdonnefort@gmail.com&gt;
Signed-off-by: Lee Jones &lt;lee.jones@linaro.org&gt;
</content>
</entry>
<entry>
<title>mfd: lpc_ich: Convert ICH GPIOs IDs to enum</title>
<updated>2014-03-19T08:58:20Z</updated>
<author>
<name>Vincent Donnefort</name>
<email>vdonnefort@gmail.com</email>
</author>
<published>2014-02-14T14:01:53Z</published>
<link rel='alternate' type='text/html' href='https://universe.0xinfinity.dev/distro/kernel/commit/?id=6cec365e3eba3dd8c864056d8d3fd9e73ab8dd7a'/>
<id>urn:sha1:6cec365e3eba3dd8c864056d8d3fd9e73ab8dd7a</id>
<content type='text'>
All those IDs are arbitrary and so can be encapsulated into an enumeration.

Signed-off-by: Vincent Donnefort &lt;vdonnefort@gmail.com&gt;
Signed-off-by: Lee Jones &lt;lee.jones@linaro.org&gt;
</content>
</entry>
<entry>
<title>gpio: gpio-ich: Share ownership of GPIO groups</title>
<updated>2012-09-14T07:52:13Z</updated>
<author>
<name>Jean Delvare</name>
<email>khali@linux-fr.org</email>
</author>
<published>2012-07-23T15:34:15Z</published>
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<id>urn:sha1:4f600ada70beeb1dfe08e11e871bf31015aa0a3d</id>
<content type='text'>
The ICH chips have their GPIO pins organized in 2 or 3 independent
groups of 32 GPIO pins. It can happen that the ACPI BIOS wants to make
use of pins in one group, preventing the OS to access these. This does
not prevent the OS from accessing the other group(s).

This is the case for example on my Asus Z8NA-D6 board. The ACPI BIOS
wants to control GPIO 18 (group 1), while I (the OS) need to control
GPIO 52 and 53 (group 2) for SMBus multiplexing.

So instead of checking for ACPI resource conflict on the whole I/O
range, check on a per-group basis, and consider it a success if at
least one of the groups is available for the OS to use.

Signed-off-by: Jean Delvare &lt;khali@linux-fr.org&gt;
Cc: Peter Tyser &lt;ptyser@xes-inc.com&gt;
Cc: Aaron Sierra &lt;asierra@xes-inc.com&gt;
Cc: Grant Likely &lt;grant.likely@secretlab.ca&gt;
Acked-by: Linus Walleij &lt;linus.walleij@linaro.org&gt;
Signed-off-by: Samuel Ortiz &lt;sameo@linux.intel.com&gt;
</content>
</entry>
<entry>
<title>watchdog: Convert iTCO_wdt driver to mfd model</title>
<updated>2012-05-09T15:20:09Z</updated>
<author>
<name>Aaron Sierra</name>
<email>asierra@xes-inc.com</email>
</author>
<published>2012-04-20T19:14:11Z</published>
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<id>urn:sha1:887c8ec7219fc8eba78bb8f44a74c660934e9b98</id>
<content type='text'>
This patch converts the iTCO_wdt driver to use the multi-function device
driver model. It uses resources discovered by the lpc_ich driver, so that
it no longer does its own PCI scanning.

Signed-off-by: Aaron Sierra &lt;asierra@xes-inc.com&gt;
Signed-off-by: Guenter Roeck &lt;linux@roeck-us.net&gt;
Signed-off-by: Samuel Ortiz &lt;sameo@linux.intel.com&gt;
</content>
</entry>
<entry>
<title>mfd: Add LPC driver for Intel ICH chipsets</title>
<updated>2012-05-01T10:00:21Z</updated>
<author>
<name>Aaron Sierra</name>
<email>asierra@xes-inc.com</email>
</author>
<published>2012-03-28T14:43:10Z</published>
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<id>urn:sha1:4630b130b30be6420394ba31121e111c8771ca08</id>
<content type='text'>
This driver currently creates resources for use by a forthcoming ICH
chipset GPIO driver. It could be expanded to create the resources for
converting the esb2rom (mtd) and iTCO_wdt (wdt), and potentially more,
drivers to use the mfd model.

Signed-off-by: Aaron Sierra &lt;asierra@xes-inc.com&gt;
Signed-off-by: Guenter Roeck &lt;linux@roeck-us.net&gt;
Signed-off-by: Samuel Ortiz &lt;sameo@linux.intel.com&gt;
</content>
</entry>
</feed>
