kernel/include/linux/mfd/intel-m10-bmc.h, branch linux-6.2.y

mfd: intel-m10-bmc: Add support for MAX10 BMC Secure Updates

2021-04-14T15:06:57Z

Add macros and definitions required by the MAX10 BMC Secure Update driver. Signed-off-by: Russ Weight Signed-off-by: Lee Jones

mfd: intel-m10-bmc: Add access table configuration to the regmap

2021-04-14T15:03:41Z

This patch adds access tables to the MAX 10 BMC regmap. This prevents the host from accessing the unwanted I/O space. It also filters out the invalid outputs when reading the regmap debugfs interface. Signed-off-by: Matthew Gerlach Signed-off-by: Xu Yilun Reviewed-by: Tom Rix Signed-off-by: Lee Jones

mfd: intel-m10-bmc: Simplify the legacy version reg definition

2021-04-14T15:03:39Z

The version register is the only one in the legacy I/O space to be accessed, so it is not necessary to define the legacy base & version register offset. A direct definition of the legacy version register address would be fine. Signed-off-by: Xu Yilun Reviewed-by: Tom Rix Signed-off-by: Lee Jones

mfd: intel-m10-bmc: Fix the register access range

2021-04-14T15:03:37Z

This patch fixes the max register address of MAX 10 BMC. The range 0x20000000 ~ 0x200000fc are for control registers of the QSPI flash controller, which are not accessible to host. Signed-off-by: Xu Yilun Reviewed-by: Tom Rix Signed-off-by: Lee Jones

mfd: intel-m10-bmc: Expose MAC address and count

2021-02-08T13:54:25Z

Create two sysfs entries for exposing the MAC address and count from the MAX10 BMC register space. The MAC address is the first in a sequential block of MAC addresses reserved for the FPGA card. The MAC count is the number of MAC addresses in the reserved block. Signed-off-by: Russ Weight Signed-off-by: Xu Yilun Signed-off-by: Lee Jones

mfd: intel-m10-bmc: Add Intel MAX 10 BMC chip support for Intel FPGA PAC

2020-09-30T16:46:21Z

This patch implements the basic functions of the BMC chip for some Intel FPGA PCIe Acceleration Cards (PAC). The BMC is implemented using the Intel MAX 10 CPLD. This BMC chip is connected to the FPGA by a SPI bus. To provide direct register access from the FPGA, the "SPI slave to Avalon Master Bridge" (spi-avmm) IP is integrated in the chip. It converts encoded streams of bytes from the host to the internal register read/write on the Avalon bus. So This driver uses the regmap-spi-avmm for register accessing. Signed-off-by: Xu Yilun Signed-off-by: Wu Hao Signed-off-by: Matthew Gerlach Signed-off-by: Russ Weight Reviewed-by: Tom Rix Signed-off-by: Lee Jones