mfd: intel-m10-bmc: Fix the register access range

2021-05-12T06:37:29Z

[ Upstream commit d9b326b2c3673f939941806146aee38e5c635fd0 ] This patch fixes the max register address of MAX 10 BMC. The range 0x20000000 ~ 0x200000fc are for control registers of the QSPI flash controller, which are not accessible to host. Signed-off-by: Xu Yilun Reviewed-by: Tom Rix Signed-off-by: Lee Jones Signed-off-by: Sasha Levin

mfd: intel-m10-bmc: Add Intel MAX 10 BMC chip support for Intel FPGA PAC

2020-09-30T16:46:21Z

This patch implements the basic functions of the BMC chip for some Intel FPGA PCIe Acceleration Cards (PAC). The BMC is implemented using the Intel MAX 10 CPLD. This BMC chip is connected to the FPGA by a SPI bus. To provide direct register access from the FPGA, the "SPI slave to Avalon Master Bridge" (spi-avmm) IP is integrated in the chip. It converts encoded streams of bytes from the host to the internal register read/write on the Avalon bus. So This driver uses the regmap-spi-avmm for register accessing. Signed-off-by: Xu Yilun Signed-off-by: Wu Hao Signed-off-by: Matthew Gerlach Signed-off-by: Russ Weight Reviewed-by: Tom Rix Signed-off-by: Lee Jones

kernel/include/linux/mfd/intel-m10-bmc.h, branch linux-5.11.y

mfd: intel-m10-bmc: Fix the register access range

mfd: intel-m10-bmc: Add Intel MAX 10 BMC chip support for Intel FPGA PAC