<feed xmlns='http://www.w3.org/2005/Atom'>
<title>kernel/include/linux/mailbox, branch linux-6.17.y</title>
<subtitle>Hosts the 0x221E linux distro kernel.</subtitle>
<id>https://universe.0xinfinity.dev/distro/kernel/atom?h=linux-6.17.y</id>
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<updated>2025-12-06T21:27:33Z</updated>
<entry>
<title>mailbox: mtk-cmdq: Refine DMA address handling for the command buffer</title>
<updated>2025-12-06T21:27:33Z</updated>
<author>
<name>Jason-JH Lin</name>
<email>jason-jh.lin@mediatek.com</email>
</author>
<published>2025-10-22T17:16:30Z</published>
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<id>urn:sha1:26cc0fcbc543e6be200647a22be2cdb19978c3b6</id>
<content type='text'>
[ Upstream commit a195c7ccfb7a21b8118139835e25936ec8722596 ]

GCE can only fetch the command buffer address from a 32-bit register.
Some SoCs support a 35-bit command buffer address for GCE, which
requires a right shift of 3 bits before setting the address into
the 32-bit register. A comment has been added to the header of
cmdq_get_shift_pa() to explain this requirement.

To prevent the GCE command buffer address from being DMA mapped beyond
its supported bit range, the DMA bit mask for the device is set during
initialization.

Additionally, to ensure the correct shift is applied when setting or
reading the register that stores the GCE command buffer address,
new APIs, cmdq_convert_gce_addr() and cmdq_revert_gce_addr(), have
been introduced for consistent operations on this register.

The variable type for the command buffer address has been standardized
to dma_addr_t to prevent handling issues caused by type mismatches.

Fixes: 0858fde496f8 ("mailbox: cmdq: variablize address shift in platform")
Signed-off-by: Jason-JH Lin &lt;jason-jh.lin@mediatek.com&gt;
Reviewed-by: AngeloGioacchino Del Regno &lt;angelogioacchino.delregno@collabora.com&gt;
Signed-off-by: Jassi Brar &lt;jassisinghbrar@gmail.com&gt;
Signed-off-by: Sasha Levin &lt;sashal@kernel.org&gt;
</content>
</entry>
<entry>
<title>mailbox: mtk-cmdq: remove cl in struct cmdq_pkt</title>
<updated>2025-03-27T01:58:24Z</updated>
<author>
<name>Chun-Kuang Hu</name>
<email>chunkuang.hu@kernel.org</email>
</author>
<published>2025-02-09T02:11:02Z</published>
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<id>urn:sha1:98bbabbc12dce03da8473edd0bc8d7072d723769</id>
<content type='text'>
Every client driver has the struct cmdq_client information, so
it's not necessary to store it in struct cmdq_pkt. cl is used to
store struct cmdq_client information and now no client driver use
it, so remove it.

Signed-off-by: Chun-Kuang Hu &lt;chunkuang.hu@kernel.org&gt;
Signed-off-by: Jassi Brar &lt;jassisinghbrar@gmail.com&gt;
</content>
</entry>
<entry>
<title>mailbox: add Samsung Exynos driver</title>
<updated>2025-01-18T22:18:48Z</updated>
<author>
<name>Tudor Ambarus</name>
<email>tudor.ambarus@linaro.org</email>
</author>
<published>2025-01-15T14:18:15Z</published>
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<id>urn:sha1:fbf7e5ce408e0619072e84e93e875de52f2b5fa5</id>
<content type='text'>
The Samsung Exynos mailbox controller, used on Google GS101 SoC, has 16
flag bits for hardware interrupt generation and a shared register for
passing mailbox messages. When the controller is used by the
ACPM interface the shared register is ignored and the mailbox controller
acts as a doorbell. The controller just raises the interrupt to APM
after the ACPM interface has written the message to SRAM.

Add support for the Samsung Exynos mailbox controller.

Signed-off-by: Tudor Ambarus &lt;tudor.ambarus@linaro.org&gt;
Signed-off-by: Jassi Brar &lt;jassisinghbrar@gmail.com&gt;
</content>
</entry>
<entry>
<title>mailbox: add Microchip IPC support</title>
<updated>2025-01-18T22:09:48Z</updated>
<author>
<name>Valentina Fernandez</name>
<email>valentina.fernandezalanis@microchip.com</email>
</author>
<published>2024-12-17T11:31:34Z</published>
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<id>urn:sha1:e4b1d67e71419c4af581890ecea84b04920d4116</id>
<content type='text'>
Add a mailbox controller driver for the Microchip Inter-processor
Communication (IPC), which is used to send and receive data between
processors.

The driver uses the RISC-V Supervisor Binary Interface (SBI) to
communicate with software running in machine mode (M-mode) to access
the IPC hardware block.

Additional details on the Microchip vendor extension and the IPC
function IDs described in the driver can be found in the following
documentation:

https://github.com/linux4microchip/microchip-sbi-ecall-extension

This SBI interface in this driver is compatible with the Mi-V Inter-hart
Communication (IHC) IP.

Transmitting and receiving data through the mailbox framework is done
through struct mchp_ipc_msg.

Signed-off-by: Valentina Fernandez &lt;valentina.fernandezalanis@microchip.com&gt;
Signed-off-by: Jassi Brar &lt;jassisinghbrar@gmail.com&gt;
</content>
</entry>
<entry>
<title>mailbox: zynqmp: Fix typo in IPI documentation</title>
<updated>2023-03-14T19:28:12Z</updated>
<author>
<name>Tanmay Shah</name>
<email>tanmay.shah@amd.com</email>
</author>
<published>2023-03-11T01:24:06Z</published>
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<id>urn:sha1:79963fbfc233759bd8a43462f120d15a1bd4f4fa</id>
<content type='text'>
Xilinx IPI message buffers allows 32-byte data transfer.
Fix documentation that says 12 bytes

Fixes: 4981b82ba2ff ("mailbox: ZynqMP IPI mailbox controller")
Signed-off-by: Tanmay Shah &lt;tanmay.shah@amd.com&gt;
Acked-by: Michal Simek &lt;michal.simek@amd.com&gt;
Cc: stable@vger.kernel.org
Link: https://lore.kernel.org/r/20230311012407.1292118-4-tanmay.shah@amd.com
Signed-off-by: Mathieu Poirier &lt;mathieu.poirier@linaro.org&gt;
</content>
</entry>
<entry>
<title>mailbox: mtk-cmdq: Remove proprietary cmdq_task_cb</title>
<updated>2022-08-02T20:06:57Z</updated>
<author>
<name>Chun-Kuang Hu</name>
<email>chunkuang.hu@kernel.org</email>
</author>
<published>2022-06-08T14:40:55Z</published>
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<id>urn:sha1:d9c26e0a58b0039d1ad4340d826fe8db866e9455</id>
<content type='text'>
rx_callback is a standard mailbox callback mechanism and could cover the
function of proprietary cmdq_task_cb, so use the standard one instead of
the proprietary one. Client driver has changed to use standard
rx_callback, so remove proprietary cmdq_task_cb.

Signed-off-by: Chun-Kuang Hu &lt;chunkuang.hu@kernel.org&gt;
Reviewed-by: Matthias Brugger &lt;matthias.bgg@gmail.com&gt;
Signed-off-by: Jassi Brar &lt;jaswinder.singh@linaro.org&gt;
</content>
</entry>
<entry>
<title>mailbox: mtk-cmdq: Add struct cmdq_pkt in struct cmdq_cb_data</title>
<updated>2021-06-26T16:40:20Z</updated>
<author>
<name>Chun-Kuang Hu</name>
<email>chunkuang.hu@kernel.org</email>
</author>
<published>2021-03-14T23:33:23Z</published>
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<id>urn:sha1:8ebc3b5aa4cfafd8b9d58e2595a12f0715594619</id>
<content type='text'>
Current client use 'struct cmdq_pkt' as callback data, so
change 'void *data' to 'struct cmdq_pkt *pkt'. Keep data
until client use pkt instead of data.

Signed-off-by: Chun-Kuang Hu &lt;chunkuang.hu@kernel.org&gt;
Reviewed-by: Yongqiang Niu &lt;yongqiang.niu@mediatek.com&gt;
Signed-off-by: Jassi Brar &lt;jaswinder.singh@linaro.org&gt;
</content>
</entry>
<entry>
<title>mailbox: mtk-cmdq: Remove cmdq_cb_status</title>
<updated>2021-06-26T16:39:54Z</updated>
<author>
<name>Chun-Kuang Hu</name>
<email>chunkuang.hu@kernel.org</email>
</author>
<published>2021-03-14T23:33:21Z</published>
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<id>urn:sha1:b3c0d72b092e52ae7369b52fb97f63eb2ea7f16a</id>
<content type='text'>
cmdq_cb_status is an error status. Use the standard error number
instead of cmdq_cb_status to prevent status duplication.

Signed-off-by: Chun-Kuang Hu &lt;chunkuang.hu@kernel.org&gt;
Reviewed-by: Yongqiang Niu &lt;yongqiang.niu@mediatek.com&gt;
Signed-off-by: Jassi Brar &lt;jaswinder.singh@linaro.org&gt;
</content>
</entry>
<entry>
<title>mailbox: arm_mhuv2: Add driver</title>
<updated>2020-12-10T01:26:02Z</updated>
<author>
<name>Viresh Kumar</name>
<email>viresh.kumar@linaro.org</email>
</author>
<published>2020-11-17T10:02:06Z</published>
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<id>urn:sha1:5a6338cce9f4133c478d3b10b300f96dd644379a</id>
<content type='text'>
This adds driver for the ARM MHUv2 (Message Handling Unit) mailbox
controller.

This is based on the accepted DT bindings of the controller and supports
combination of both transport protocols, i.e. doorbell and data-transfer.

Transmitting and receiving data through the mailbox framework is done
through struct arm_mhuv2_mbox_msg.

Based on the initial work done by Morten Borup Petersen from ARM.

Co-developed-by: Tushar Khandelwal &lt;tushar.khandelwal@arm.com&gt;
Signed-off-by: Tushar Khandelwal &lt;tushar.khandelwal@arm.com&gt;
Tested-by: Usama Arif &lt;usama.arif@arm.com&gt;
Signed-off-by: Viresh Kumar &lt;viresh.kumar@linaro.org&gt;
Signed-off-by: Jassi Brar &lt;jaswinder.singh@linaro.org&gt;
</content>
</entry>
<entry>
<title>mailbox: zynqmp-ipi-message: Replace zero-length array with flexible-array member</title>
<updated>2020-10-29T22:22:59Z</updated>
<author>
<name>Gustavo A. R. Silva</name>
<email>gustavoars@kernel.org</email>
</author>
<published>2020-08-31T15:19:18Z</published>
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<id>urn:sha1:277ffd6c1ec0aa60856a03e18455fcca7d2a1186</id>
<content type='text'>
There is a regular need in the kernel to provide a way to declare having a
dynamically sized set of trailing elements in a structure. Kernel code should
always use “flexible array members”[1] for these cases. The older style of
one-element or zero-length arrays should no longer be used[2].

[1] https://en.wikipedia.org/wiki/Flexible_array_member
[2] https://www.kernel.org/doc/html/v5.9-rc1/process/deprecated.html#zero-length-and-one-element-arrays

Signed-off-by: Gustavo A. R. Silva &lt;gustavoars@kernel.org&gt;
</content>
</entry>
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