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<title>kernel/include/linux/mailbox/mtk-cmdq-mailbox.h, branch master</title>
<subtitle>Hosts the 0x221E linux distro kernel.</subtitle>
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<updated>2026-01-19T11:57:45Z</updated>
<entry>
<title>mailbox: mtk-cmdq: Add mminfra_offset configuration for DRAM transaction</title>
<updated>2026-01-19T11:57:45Z</updated>
<author>
<name>Jason-JH Lin</name>
<email>jason-jh.lin@mediatek.com</email>
</author>
<published>2025-10-31T15:56:32Z</published>
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<id>urn:sha1:1c1874843bc43d9f333d441af00f61ece2373e5d</id>
<content type='text'>
The GCE in MT8196 is placed in MMINFRA and requires all addresses
in GCE instructions for DRAM transactions to be IOVA.

Due to MMIO, if the GCE needs to access a hardware register at
0x1000_0000, but the SMMU is also mapping a DRAM block at 0x1000_0000,
the MMINFRA will not know whether to write to the hardware register or
the DRAM.
To solve this, MMINFRA treats addresses greater than 2G as data paths
and those less than 2G as config paths because the DRAM start address
is currently at 2G (0x8000_0000). On the data path, MMINFRA remaps
DRAM addresses by subtracting 2G, allowing SMMU to map DRAM addresses
less than 2G.
For example, if the DRAM start address 0x8000_0000 is mapped to
IOVA=0x0, when GCE accesses IOVA=0x0, it must add a 2G offset to
the address in the GCE instruction. MMINFRA will then see it as a
data path (IOVA &gt;= 2G) and subtract 2G, allowing GCE to access IOVA=0x0.

Since the MMINFRA remap subtracting 2G is done in hardware and cannot
be configured by software, the address of DRAM in GCE instruction must
always add 2G to ensure proper access. After that, the shift functions
do more than just shift addresses, so the APIs were renamed to
cmdq_convert_gce_addr() and cmdq_revert_gce_addr().

This 2G adjustment is referred to as mminfra_offset in the CMDQ driver.
CMDQ helper can get the mminfra_offset from the cmdq_mbox_priv of
cmdq_pkt and add the mminfra_offset to the DRAM address in GCE
instructions.

Signed-off-by: Jason-JH Lin &lt;jason-jh.lin@mediatek.com&gt;
Reviewed-by: AngeloGioacchino Del Regno &lt;angelogioacchino.delregno@collabora.com&gt;
Acked-by: Jassi Brar &lt;jassisinghbrar@gmail.com&gt;
Acked-by: AngeloGioacchino Del Regno &lt;angelogioacchino.delregno@collabora.com&gt;
Signed-off-by: AngeloGioacchino Del Regno &lt;angelogioacchino.delregno@collabora.com&gt;
</content>
</entry>
<entry>
<title>mailbox: mtk-cmdq: Add cmdq private data to cmdq_pkt for generating instruction</title>
<updated>2026-01-19T11:57:44Z</updated>
<author>
<name>Jason-JH Lin</name>
<email>jason-jh.lin@mediatek.com</email>
</author>
<published>2025-10-31T15:56:30Z</published>
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<id>urn:sha1:266f35701b6f7ddd9521310eb5add01001d4a614</id>
<content type='text'>
Add the cmdq_mbox_priv structure to store the private data of GCE,
such as the shift bits of the physical address. Then, include the
cmdq_mbox_priv structure within the cmdq_pkt structure.

This allows CMDQ users to utilize the private data in cmdq_pkt to
generate GCE instructions when needed. Additionally, having
cmdq_mbox_priv makes it easier to expand and reference other GCE
private data in the future.

Add cmdq_get_mbox_priv() for CMDQ users to get all the private data
into the cmdq_mbox_priv of the cmdq_pkt.

Signed-off-by: Jason-JH Lin &lt;jason-jh.lin@mediatek.com&gt;
Reviewed-by: AngeloGioacchino Del Regno &lt;angelogioacchino.delregno@collabora.com&gt;
Acked-by: Jassi Brar &lt;jassisinghbrar@gmail.com&gt;
Acked-by: AngeloGioacchino Del Regno &lt;angelogioacchino.delregno@collabora.com&gt;
Signed-off-by: AngeloGioacchino Del Regno &lt;angelogioacchino.delregno@collabora.com&gt;
</content>
</entry>
<entry>
<title>mailbox: mtk-cmdq: Refine DMA address handling for the command buffer</title>
<updated>2025-11-28T15:31:53Z</updated>
<author>
<name>Jason-JH Lin</name>
<email>jason-jh.lin@mediatek.com</email>
</author>
<published>2025-10-22T17:16:30Z</published>
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<id>urn:sha1:a195c7ccfb7a21b8118139835e25936ec8722596</id>
<content type='text'>
GCE can only fetch the command buffer address from a 32-bit register.
Some SoCs support a 35-bit command buffer address for GCE, which
requires a right shift of 3 bits before setting the address into
the 32-bit register. A comment has been added to the header of
cmdq_get_shift_pa() to explain this requirement.

To prevent the GCE command buffer address from being DMA mapped beyond
its supported bit range, the DMA bit mask for the device is set during
initialization.

Additionally, to ensure the correct shift is applied when setting or
reading the register that stores the GCE command buffer address,
new APIs, cmdq_convert_gce_addr() and cmdq_revert_gce_addr(), have
been introduced for consistent operations on this register.

The variable type for the command buffer address has been standardized
to dma_addr_t to prevent handling issues caused by type mismatches.

Fixes: 0858fde496f8 ("mailbox: cmdq: variablize address shift in platform")
Signed-off-by: Jason-JH Lin &lt;jason-jh.lin@mediatek.com&gt;
Reviewed-by: AngeloGioacchino Del Regno &lt;angelogioacchino.delregno@collabora.com&gt;
Signed-off-by: Jassi Brar &lt;jassisinghbrar@gmail.com&gt;
</content>
</entry>
<entry>
<title>mailbox: mtk-cmdq: remove cl in struct cmdq_pkt</title>
<updated>2025-03-27T01:58:24Z</updated>
<author>
<name>Chun-Kuang Hu</name>
<email>chunkuang.hu@kernel.org</email>
</author>
<published>2025-02-09T02:11:02Z</published>
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<id>urn:sha1:98bbabbc12dce03da8473edd0bc8d7072d723769</id>
<content type='text'>
Every client driver has the struct cmdq_client information, so
it's not necessary to store it in struct cmdq_pkt. cl is used to
store struct cmdq_client information and now no client driver use
it, so remove it.

Signed-off-by: Chun-Kuang Hu &lt;chunkuang.hu@kernel.org&gt;
Signed-off-by: Jassi Brar &lt;jassisinghbrar@gmail.com&gt;
</content>
</entry>
<entry>
<title>mailbox: mtk-cmdq: Remove proprietary cmdq_task_cb</title>
<updated>2022-08-02T20:06:57Z</updated>
<author>
<name>Chun-Kuang Hu</name>
<email>chunkuang.hu@kernel.org</email>
</author>
<published>2022-06-08T14:40:55Z</published>
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<id>urn:sha1:d9c26e0a58b0039d1ad4340d826fe8db866e9455</id>
<content type='text'>
rx_callback is a standard mailbox callback mechanism and could cover the
function of proprietary cmdq_task_cb, so use the standard one instead of
the proprietary one. Client driver has changed to use standard
rx_callback, so remove proprietary cmdq_task_cb.

Signed-off-by: Chun-Kuang Hu &lt;chunkuang.hu@kernel.org&gt;
Reviewed-by: Matthias Brugger &lt;matthias.bgg@gmail.com&gt;
Signed-off-by: Jassi Brar &lt;jaswinder.singh@linaro.org&gt;
</content>
</entry>
<entry>
<title>mailbox: mtk-cmdq: Add struct cmdq_pkt in struct cmdq_cb_data</title>
<updated>2021-06-26T16:40:20Z</updated>
<author>
<name>Chun-Kuang Hu</name>
<email>chunkuang.hu@kernel.org</email>
</author>
<published>2021-03-14T23:33:23Z</published>
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<id>urn:sha1:8ebc3b5aa4cfafd8b9d58e2595a12f0715594619</id>
<content type='text'>
Current client use 'struct cmdq_pkt' as callback data, so
change 'void *data' to 'struct cmdq_pkt *pkt'. Keep data
until client use pkt instead of data.

Signed-off-by: Chun-Kuang Hu &lt;chunkuang.hu@kernel.org&gt;
Reviewed-by: Yongqiang Niu &lt;yongqiang.niu@mediatek.com&gt;
Signed-off-by: Jassi Brar &lt;jaswinder.singh@linaro.org&gt;
</content>
</entry>
<entry>
<title>mailbox: mtk-cmdq: Remove cmdq_cb_status</title>
<updated>2021-06-26T16:39:54Z</updated>
<author>
<name>Chun-Kuang Hu</name>
<email>chunkuang.hu@kernel.org</email>
</author>
<published>2021-03-14T23:33:21Z</published>
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<id>urn:sha1:b3c0d72b092e52ae7369b52fb97f63eb2ea7f16a</id>
<content type='text'>
cmdq_cb_status is an error status. Use the standard error number
instead of cmdq_cb_status to prevent status duplication.

Signed-off-by: Chun-Kuang Hu &lt;chunkuang.hu@kernel.org&gt;
Reviewed-by: Yongqiang Niu &lt;yongqiang.niu@mediatek.com&gt;
Signed-off-by: Jassi Brar &lt;jaswinder.singh@linaro.org&gt;
</content>
</entry>
<entry>
<title>soc: mediatek: cmdq: add clear option in cmdq_pkt_wfe api</title>
<updated>2020-09-25T15:27:39Z</updated>
<author>
<name>Dennis YC Hsieh</name>
<email>dennis-yc.hsieh@mediatek.com</email>
</author>
<published>2020-07-07T15:45:13Z</published>
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<id>urn:sha1:23c22299cd290409c6b78f57c42b64f8dfb6dd92</id>
<content type='text'>
Add clear parameter to let client decide if
event should be clear to 0 after GCE receive it.

Signed-off-by: Dennis YC Hsieh &lt;dennis-yc.hsieh@mediatek.com&gt;
Acked-by: Chun-Kuang Hu &lt;chunkuang.hu@kernel.org&gt;
Link: https://lore.kernel.org/r/1594136714-11650-9-git-send-email-dennis-yc.hsieh@mediatek.com
[mb: fix commit message]
Signed-off-by: Matthias Brugger &lt;matthias.bgg@gmail.com&gt;
</content>
</entry>
<entry>
<title>soc: mediatek: cmdq: add read_s function</title>
<updated>2020-09-25T15:27:34Z</updated>
<author>
<name>Dennis YC Hsieh</name>
<email>dennis-yc.hsieh@mediatek.com</email>
</author>
<published>2020-07-07T15:45:09Z</published>
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<id>urn:sha1:d3b04aab06fbc33ddea15725f3ff1667c9717929</id>
<content type='text'>
Add read_s function in cmdq helper functions which support read value from
register or dma physical address into gce internal register.

Signed-off-by: Dennis YC Hsieh &lt;dennis-yc.hsieh@mediatek.com&gt;
Link: https://lore.kernel.org/r/1594136714-11650-5-git-send-email-dennis-yc.hsieh@mediatek.com
Signed-off-by: Matthias Brugger &lt;matthias.bgg@gmail.com&gt;
</content>
</entry>
<entry>
<title>soc: mediatek: cmdq: add write_s_mask function</title>
<updated>2020-09-25T15:27:32Z</updated>
<author>
<name>Dennis YC Hsieh</name>
<email>dennis-yc.hsieh@mediatek.com</email>
</author>
<published>2020-07-07T15:45:08Z</published>
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<id>urn:sha1:11c7842d41c82eb3551a0606ccba89ac33318b62</id>
<content type='text'>
add write_s_mask function in cmdq helper functions which
writes value contains in internal register to address
with mask and large dma access support.

Signed-off-by: Dennis YC Hsieh &lt;dennis-yc.hsieh@mediatek.com&gt;
Link: https://lore.kernel.org/r/1594136714-11650-4-git-send-email-dennis-yc.hsieh@mediatek.com
Signed-off-by: Matthias Brugger &lt;matthias.bgg@gmail.com&gt;
</content>
</entry>
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