<feed xmlns='http://www.w3.org/2005/Atom'>
<title>kernel/include/linux/irqdomain_defs.h, branch linux-rolling-stable</title>
<subtitle>Hosts the 0x221E linux distro kernel.</subtitle>
<id>https://universe.0xinfinity.dev/distro/kernel/atom?h=linux-rolling-stable</id>
<link rel='self' href='https://universe.0xinfinity.dev/distro/kernel/atom?h=linux-rolling-stable'/>
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<updated>2024-05-15T22:02:08Z</updated>
<entry>
<title>Revert "genirq/msi: Provide constants for PCI/IMS support"</title>
<updated>2024-05-15T22:02:08Z</updated>
<author>
<name>Bjorn Helgaas</name>
<email>bhelgaas@google.com</email>
</author>
<published>2024-04-10T22:13:07Z</published>
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<id>urn:sha1:8a1940bca94bbf060bba4fc4f69c37270d5828f8</id>
<content type='text'>
This reverts commit e23d4192bf9b612bce5b24f22719fd3cc6edaa69.

IMS (Interrupt Message Store) support appeared in v6.2, but there are no
users yet.

Remove it for now.  We can add it back when a user comes along.

Link: https://lore.kernel.org/r/20240410221307.2162676-8-helgaas@kernel.org
Signed-off-by: Bjorn Helgaas &lt;bhelgaas@google.com&gt;
Reviewed-by: Kevin Tian &lt;kevin.tian@intel.com&gt;
Reviewed-by: Thomas Gleixner &lt;tglx@linutronix.de&gt;
</content>
</entry>
<entry>
<title>genirq/msi: Provide DOMAIN_BUS_WIRED_TO_MSI</title>
<updated>2024-02-15T16:55:40Z</updated>
<author>
<name>Thomas Gleixner</name>
<email>tglx@linutronix.de</email>
</author>
<published>2024-01-27T16:17:37Z</published>
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<id>urn:sha1:2d566a498d6483ba986dadc496f64a20b032608f</id>
<content type='text'>
Provide a domain bus token for the upcoming support for wire to MSI device
domains so the domain can be distinguished from regular device MSI domains.

Signed-off-by: Thomas Gleixner &lt;tglx@linutronix.de&gt;
Signed-off-by: Anup Patel &lt;apatel@ventanamicro.com&gt;
Signed-off-by: Thomas Gleixner &lt;tglx@linutronix.de&gt;
Link: https://lore.kernel.org/r/20240127161753.114685-10-apatel@ventanamicro.com

</content>
</entry>
<entry>
<title>genirq/irqdomain: Add DOMAIN_BUS_DEVICE_MSI</title>
<updated>2024-02-15T16:55:40Z</updated>
<author>
<name>Thomas Gleixner</name>
<email>tglx@linutronix.de</email>
</author>
<published>2024-01-27T16:17:32Z</published>
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<id>urn:sha1:6516d5a295356f8fd5827a1c0954d7ed5b2324dd</id>
<content type='text'>
Add a new domain bus token to prepare for device MSI which aims to replace
the existing platform MSI maze.

Signed-off-by: Thomas Gleixner &lt;tglx@linutronix.de&gt;
Signed-off-by: Anup Patel &lt;apatel@ventanamicro.com&gt;
Signed-off-by: Thomas Gleixner &lt;tglx@linutronix.de&gt;
Link: https://lore.kernel.org/r/20240127161753.114685-5-apatel@ventanamicro.com

</content>
</entry>
<entry>
<title>genirq/msi: Provide constants for PCI/IMS support</title>
<updated>2022-12-05T21:22:34Z</updated>
<author>
<name>Thomas Gleixner</name>
<email>tglx@linutronix.de</email>
</author>
<published>2022-11-24T23:26:28Z</published>
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<id>urn:sha1:e23d4192bf9b612bce5b24f22719fd3cc6edaa69</id>
<content type='text'>
Provide the necessary constants for PCI/IMS support:

  - A new bus token for MSI irqdomain identification
  - A MSI feature flag for the MSI irqdomains to signal support
  - A secondary domain id

The latter expands the device internal domain pointer storage array from 1
to 2 entries. That extra pointer is mostly unused today, but the
alternative solutions would not be free either and would introduce more
complexity all over the place. Trade the 8bytes for simplicity.

Signed-off-by: Thomas Gleixner &lt;tglx@linutronix.de&gt;
Reviewed-by: Kevin Tian &lt;kevin.tian@intel.com&gt;
Acked-by: Marc Zyngier &lt;maz@kernel.org&gt;
Link: https://lore.kernel.org/r/20221124232326.846169830@linutronix.de

</content>
</entry>
<entry>
<title>iommu/amd: Switch to MSI base domains</title>
<updated>2022-12-05T21:22:33Z</updated>
<author>
<name>Thomas Gleixner</name>
<email>tglx@linutronix.de</email>
</author>
<published>2022-11-24T23:26:10Z</published>
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<id>urn:sha1:cc7594ffadde77e2825faf1c576230530c829bc3</id>
<content type='text'>
Remove the global PCI/MSI irqdomain implementation and provide the required
MSI parent ops so the PCI/MSI code can detect the new parent and setup per
device domains.

Signed-off-by: Thomas Gleixner &lt;tglx@linutronix.de&gt;
Reviewed-by: Kevin Tian &lt;kevin.tian@intel.com&gt;
Acked-by: Marc Zyngier &lt;maz@kernel.org&gt;
Link: https://lore.kernel.org/r/20221124232326.209212272@linutronix.de

</content>
</entry>
<entry>
<title>iommu/vt-d: Switch to MSI parent domains</title>
<updated>2022-12-05T21:22:33Z</updated>
<author>
<name>Thomas Gleixner</name>
<email>tglx@linutronix.de</email>
</author>
<published>2022-11-24T23:26:08Z</published>
<link rel='alternate' type='text/html' href='https://universe.0xinfinity.dev/distro/kernel/commit/?id=9a945234abea27d45f8d89e1a1b35ab5bf41dd01'/>
<id>urn:sha1:9a945234abea27d45f8d89e1a1b35ab5bf41dd01</id>
<content type='text'>
Remove the global PCI/MSI irqdomain implementation and provide the required
MSI parent ops so the PCI/MSI code can detect the new parent and setup per
device domains.

Signed-off-by: Thomas Gleixner &lt;tglx@linutronix.de&gt;
Reviewed-by: Kevin Tian &lt;kevin.tian@intel.com&gt;
Acked-by: Marc Zyngier &lt;maz@kernel.org&gt;
Link: https://lore.kernel.org/r/20221124232326.151226317@linutronix.de

</content>
</entry>
<entry>
<title>genirq/msi: Provide BUS_DEVICE_PCI_MSI[X]</title>
<updated>2022-12-05T21:22:32Z</updated>
<author>
<name>Thomas Gleixner</name>
<email>tglx@linutronix.de</email>
</author>
<published>2022-11-24T23:26:02Z</published>
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<id>urn:sha1:bd141a3db40c877e01de8e981edb57c03199d876</id>
<content type='text'>
Provide new bus tokens for the upcoming per device PCI/MSI and PCI/MSIX
interrupt domains.

Signed-off-by: Thomas Gleixner &lt;tglx@linutronix.de&gt;
Reviewed-by: Kevin Tian &lt;kevin.tian@intel.com&gt;
Acked-by: Marc Zyngier &lt;maz@kernel.org&gt;
Link: https://lore.kernel.org/r/20221124232325.917219885@linutronix.de

</content>
</entry>
<entry>
<title>genirq/irqdomain: Move bus token enum into a seperate header</title>
<updated>2022-11-17T14:15:19Z</updated>
<author>
<name>Thomas Gleixner</name>
<email>tglx@linutronix.de</email>
</author>
<published>2022-11-11T13:54:32Z</published>
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<id>urn:sha1:aeef20527c87fed37c6f159d9eafd063a099f6ed</id>
<content type='text'>
Split the bus token defines out into a seperate header file to avoid
inclusion of irqdomain.h in msi.h.

Signed-off-by: Thomas Gleixner &lt;tglx@linutronix.de&gt;
Reviewed-by: Ashok Raj &lt;ashok.raj@intel.com&gt;
Reviewed-by: Jason Gunthorpe &lt;jgg@nvidia.com&gt;
Link: https://lore.kernel.org/r/20221111122014.237221143@linutronix.de

</content>
</entry>
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