kernel/include/linux/intel-gtt.h, branch linux-5.17.yHosts the 0x221E linux distro kernel.https://universe.0xinfinity.dev/distro/kernel/atom?h=linux-5.17.y2010-11-23T20:14:43Zdrm/i915|intel-gtt: consolidate intel-gtt.h headers2010-11-23T20:14:43ZDaniel Vetterdaniel.vetter@ffwll.ch2010-11-05T17:04:52Zurn:sha1:23ed992a5ebe6964ebe312b54142fbc5e8185cdc
... and a few other defines.
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
agp/intel: Fix cache control for Sandybridge2010-09-07T10:16:43ZZhenyu Wangzhenyuw@linux.intel.com2010-08-27T03:08:57Zurn:sha1:f8f235e5bbf4e61f3e0886a44afb1dc4cfe8f337
Sandybridge GTT has new cache control bits in PTE, which controls
graphics page cache in LLC or LLC/MLC, so we need to extend the mask
function to respect the new bits.
And set cache control to always LLC only by default on Gen6.
Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
Cc: stable@kernel.org
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>