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<title>kernel/include/linux/coresight-pmu.h, branch linux-5.1.y</title>
<subtitle>Hosts the 0x221E linux distro kernel.</subtitle>
<id>https://universe.0xinfinity.dev/distro/kernel/atom?h=linux-5.1.y</id>
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<updated>2018-04-19T15:29:41Z</updated>
<entry>
<title>coresight: Move to SPDX identifier</title>
<updated>2018-04-19T15:29:41Z</updated>
<author>
<name>Mathieu Poirier</name>
<email>mathieu.poirier@linaro.org</email>
</author>
<published>2018-04-18T22:05:18Z</published>
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<id>urn:sha1:8a9fd8323087e794f1d3cd4850b393ced048bc73</id>
<content type='text'>
Move CoreSight headers to the SPDX identifier.

Signed-off-by: Mathieu Poirier &lt;mathieu.poirier@linaro.org&gt;
Cc: Alexander Shishkin &lt;alexander.shishkin@linux.intel.com&gt;
Cc: Greg Kroah-Hartman &lt;gregkh@linuxfoundation.org&gt;
Cc: Jiri Olsa &lt;jolsa@redhat.com&gt;
Cc: Namhyung Kim &lt;namhyung@kernel.org&gt;
Cc: Peter Zijlstra &lt;peterz@infradead.org&gt;
Cc: linux-arm-kernel@lists.infradead.org
Link: http://lkml.kernel.org/r/1524089118-27595-1-git-send-email-mathieu.poirier@linaro.org
Signed-off-by: Arnaldo Carvalho de Melo &lt;acme@redhat.com&gt;
</content>
</entry>
<entry>
<title>perf: cs-etm: Fix ETMv4 CONFIGR entry in perf.data file</title>
<updated>2017-08-28T15:35:43Z</updated>
<author>
<name>Mike Leach</name>
<email>mike.leach@linaro.org</email>
</author>
<published>2017-08-02T16:22:19Z</published>
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<id>urn:sha1:df770ff0586a494fabe68ffbe2898d7df5666663</id>
<content type='text'>
The value passed into the perf.data file for the CONFIGR register in ETMv4
was incorrectly being set to the command line options/ETMv3 value.

Adds bit definitions and function to remap this value to the correct ETMv4
CONFIGR bit values for all selected options.

Signed-off-by: Mike Leach &lt;mike.leach@linaro.org&gt;
Signed-off-by: Greg Kroah-Hartman &lt;gregkh@linuxfoundation.org&gt;
</content>
</entry>
<entry>
<title>coresight: pmu: Adds return stack option to perf coresight pmu</title>
<updated>2017-08-28T14:05:48Z</updated>
<author>
<name>Mike Leach</name>
<email>mike.leach@linaro.org</email>
</author>
<published>2017-08-02T16:22:01Z</published>
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<id>urn:sha1:b97971bee55dc45420e0fe352d0b4df6e74716d4</id>
<content type='text'>
Return stack is a programmable option on some ETM and PTM hardware.
Adds the option flags to enable this from the perf event command line.

Signed-off-by: Mike Leach &lt;mike.leach@linaro.org&gt;
Signed-off-by: Mathieu Poirier &lt;mathieu.poirier@linaro.org&gt;
Signed-off-by: Greg Kroah-Hartman &lt;gregkh@linuxfoundation.org&gt;
</content>
</entry>
<entry>
<title>coresight: introducing a global trace ID function</title>
<updated>2016-02-20T22:11:01Z</updated>
<author>
<name>Mathieu Poirier</name>
<email>mathieu.poirier@linaro.org</email>
</author>
<published>2016-02-18T00:52:02Z</published>
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<id>urn:sha1:17534ceb835a1a96eb921a2a80df168723d6570a</id>
<content type='text'>
TraceID values have to be unique for all tracers and
consistent between drivers and user space.  As such
introducing a central function to be used whenever a
traceID value is required.

The patch also account for data traceIDs, which are usually
I(N) + 1.

Signed-off-by: Mathieu Poirier &lt;mathieu.poirier@linaro.org&gt;
Signed-off-by: Greg Kroah-Hartman &lt;gregkh@linuxfoundation.org&gt;
</content>
</entry>
<entry>
<title>coresight: etm-perf: new PMU driver for ETM tracers</title>
<updated>2016-02-20T22:11:01Z</updated>
<author>
<name>Mathieu Poirier</name>
<email>mathieu.poirier@linaro.org</email>
</author>
<published>2016-02-18T00:52:01Z</published>
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<id>urn:sha1:0bcbf2e30ff2271b54f54c8697a185f7d86ec6e4</id>
<content type='text'>
Perf is a well known and used tool for performance monitoring
and much more. A such it is an ideal candidate for integration
with coresight based HW tracing.

This patch introduces a PMU that represent a coresight tracer to
the Perf core.

Cc: Alexander Shishkin &lt;alexander.shishkin@linux.intel.com&gt;
Signed-off-by: Mathieu Poirier &lt;mathieu.poirier@linaro.org&gt;
Signed-off-by: Greg Kroah-Hartman &lt;gregkh@linuxfoundation.org&gt;
</content>
</entry>
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