<feed xmlns='http://www.w3.org/2005/Atom'>
<title>kernel/include/linux/ccp.h, branch linux-5.2.y</title>
<subtitle>Hosts the 0x221E linux distro kernel.</subtitle>
<id>https://universe.0xinfinity.dev/distro/kernel/atom?h=linux-5.2.y</id>
<link rel='self' href='https://universe.0xinfinity.dev/distro/kernel/atom?h=linux-5.2.y'/>
<link rel='alternate' type='text/html' href='https://universe.0xinfinity.dev/distro/kernel/'/>
<updated>2019-08-16T08:10:51Z</updated>
<entry>
<title>crypto: ccp - Add support for valid authsize values less than 16</title>
<updated>2019-08-16T08:10:51Z</updated>
<author>
<name>Gary R Hook</name>
<email>gary.hook@amd.com</email>
</author>
<published>2019-07-30T16:05:24Z</published>
<link rel='alternate' type='text/html' href='https://universe.0xinfinity.dev/distro/kernel/commit/?id=9552214366b55878d9b0958f00eea7fc61ca50a2'/>
<id>urn:sha1:9552214366b55878d9b0958f00eea7fc61ca50a2</id>
<content type='text'>
commit 9f00baf74e4b6f79a3a3dfab44fb7bb2e797b551 upstream.

AES GCM encryption allows for authsize values of 4, 8, and 12-16 bytes.
Validate the requested authsize, and retain it to save in the request
context.

Fixes: 36cf515b9bbe2 ("crypto: ccp - Enable support for AES GCM on v5 CCPs")
Cc: &lt;stable@vger.kernel.org&gt;
Signed-off-by: Gary R Hook &lt;gary.hook@amd.com&gt;
Signed-off-by: Herbert Xu &lt;herbert@gondor.apana.org.au&gt;
Signed-off-by: Greg Kroah-Hartman &lt;gregkh@linuxfoundation.org&gt;

</content>
</entry>
<entry>
<title>treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 500</title>
<updated>2019-06-19T15:09:55Z</updated>
<author>
<name>Thomas Gleixner</name>
<email>tglx@linutronix.de</email>
</author>
<published>2019-06-04T08:11:33Z</published>
<link rel='alternate' type='text/html' href='https://universe.0xinfinity.dev/distro/kernel/commit/?id=d2912cb15bdda8ba4a5dd73396ad62641af2f520'/>
<id>urn:sha1:d2912cb15bdda8ba4a5dd73396ad62641af2f520</id>
<content type='text'>
Based on 2 normalized pattern(s):

  this program is free software you can redistribute it and or modify
  it under the terms of the gnu general public license version 2 as
  published by the free software foundation

  this program is free software you can redistribute it and or modify
  it under the terms of the gnu general public license version 2 as
  published by the free software foundation #

extracted by the scancode license scanner the SPDX license identifier

  GPL-2.0-only

has been chosen to replace the boilerplate/reference in 4122 file(s).

Signed-off-by: Thomas Gleixner &lt;tglx@linutronix.de&gt;
Reviewed-by: Enrico Weigelt &lt;info@metux.net&gt;
Reviewed-by: Kate Stewart &lt;kstewart@linuxfoundation.org&gt;
Reviewed-by: Allison Randal &lt;allison@lohutok.net&gt;
Cc: linux-spdx@vger.kernel.org
Link: https://lkml.kernel.org/r/20190604081206.933168790@linutronix.de
Signed-off-by: Greg Kroah-Hartman &lt;gregkh@linuxfoundation.org&gt;
</content>
</entry>
<entry>
<title>crypto: ccp - Fix XTS-AES-128 support on v5 CCPs</title>
<updated>2017-08-04T01:27:41Z</updated>
<author>
<name>Gary R Hook</name>
<email>gary.hook@amd.com</email>
</author>
<published>2017-07-25T19:12:11Z</published>
<link rel='alternate' type='text/html' href='https://universe.0xinfinity.dev/distro/kernel/commit/?id=e652399edba99a5497f0d80f240c9075d3b43493'/>
<id>urn:sha1:e652399edba99a5497f0d80f240c9075d3b43493</id>
<content type='text'>
Version 5 CCPs have some new requirements for XTS-AES: the type field
must be specified, and the key requires 512 bits, with each part
occupying 256 bits and padded with zeroes.

cc: &lt;stable@vger.kernel.org&gt; # 4.9.x+

Signed-off-by: Gary R Hook &lt;ghook@amd.com&gt;
Signed-off-by: Herbert Xu &lt;herbert@gondor.apana.org.au&gt;
</content>
</entry>
<entry>
<title>crypto: ccp - Introduce the AMD Secure Processor device</title>
<updated>2017-07-18T09:51:19Z</updated>
<author>
<name>Brijesh Singh</name>
<email>brijesh.singh@amd.com</email>
</author>
<published>2017-07-06T14:59:14Z</published>
<link rel='alternate' type='text/html' href='https://universe.0xinfinity.dev/distro/kernel/commit/?id=720419f01832f7e697cb80480b97b2a1e96045cd'/>
<id>urn:sha1:720419f01832f7e697cb80480b97b2a1e96045cd</id>
<content type='text'>
The CCP device is part of the AMD Secure Processor. In order to expand
the usage of the AMD Secure Processor, create a framework that allows
functional components of the AMD Secure Processor to be initialized and
handled appropriately.

Signed-off-by: Brijesh Singh &lt;brijesh.singh@amd.com&gt;
Acked-by: Gary R Hook &lt;gary.hook@amd.com&gt;
Signed-off-by: Herbert Xu &lt;herbert@gondor.apana.org.au&gt;
</content>
</entry>
<entry>
<title>crypto: ccp - Fix some line spacing</title>
<updated>2017-07-18T09:50:53Z</updated>
<author>
<name>Gary R Hook</name>
<email>gary.hook@amd.com</email>
</author>
<published>2017-06-27T13:58:04Z</published>
<link rel='alternate' type='text/html' href='https://universe.0xinfinity.dev/distro/kernel/commit/?id=77af0ae44e4a74f58dd741babdacec32fc8042b1'/>
<id>urn:sha1:77af0ae44e4a74f58dd741babdacec32fc8042b1</id>
<content type='text'>
Add/remove blank lines as appropriate.

Signed-off-by: Gary R Hook &lt;gary.hook@amd.com&gt;
Signed-off-by: Herbert Xu &lt;herbert@gondor.apana.org.au&gt;
</content>
</entry>
<entry>
<title>Merge git://git.kernel.org/pub/scm/linux/kernel/git/herbert/crypto-2.6</title>
<updated>2017-04-05T13:57:07Z</updated>
<author>
<name>Herbert Xu</name>
<email>herbert@gondor.apana.org.au</email>
</author>
<published>2017-04-05T13:57:07Z</published>
<link rel='alternate' type='text/html' href='https://universe.0xinfinity.dev/distro/kernel/commit/?id=c6dc0609062c6110d04c54e24b81b503eeadb2c8'/>
<id>urn:sha1:c6dc0609062c6110d04c54e24b81b503eeadb2c8</id>
<content type='text'>
Merge the crypto tree to resolve conflict between caam changes.
</content>
</entry>
<entry>
<title>crypto: ccp - Enable support for AES GCM on v5 CCPs</title>
<updated>2017-03-24T14:02:55Z</updated>
<author>
<name>Gary R Hook</name>
<email>gary.hook@amd.com</email>
</author>
<published>2017-03-15T18:21:01Z</published>
<link rel='alternate' type='text/html' href='https://universe.0xinfinity.dev/distro/kernel/commit/?id=36cf515b9bbe298e1ce7384620f0d4ec45ad3328'/>
<id>urn:sha1:36cf515b9bbe298e1ce7384620f0d4ec45ad3328</id>
<content type='text'>
A version 5 device provides the primitive commands
required for AES GCM. This patch adds support for
en/decryption.

Signed-off-by: Gary R Hook &lt;gary.hook@amd.com&gt;
Signed-off-by: Herbert Xu &lt;herbert@gondor.apana.org.au&gt;
</content>
</entry>
<entry>
<title>crypto: ccp - Enable 3DES function on v5 CCPs</title>
<updated>2017-03-24T14:02:55Z</updated>
<author>
<name>Gary R Hook</name>
<email>gary.hook@amd.com</email>
</author>
<published>2017-03-15T18:20:52Z</published>
<link rel='alternate' type='text/html' href='https://universe.0xinfinity.dev/distro/kernel/commit/?id=990672d48515ce09c76fcf1ceccee48b0dd1942b'/>
<id>urn:sha1:990672d48515ce09c76fcf1ceccee48b0dd1942b</id>
<content type='text'>
Wire up support for Triple DES in ECB mode.

Signed-off-by: Gary R Hook &lt;gary.hook@amd.com&gt;
Signed-off-by: Herbert Xu &lt;herbert@gondor.apana.org.au&gt;
</content>
</entry>
<entry>
<title>crypto: ccp - Add SHA-2 384- and 512-bit support</title>
<updated>2017-03-24T14:02:54Z</updated>
<author>
<name>Gary R Hook</name>
<email>gary.hook@amd.com</email>
</author>
<published>2017-03-15T18:20:43Z</published>
<link rel='alternate' type='text/html' href='https://universe.0xinfinity.dev/distro/kernel/commit/?id=ccebcf3f224a44ec8e9c5bfca9d8e5d29298a5a8'/>
<id>urn:sha1:ccebcf3f224a44ec8e9c5bfca9d8e5d29298a5a8</id>
<content type='text'>
Incorporate 384-bit and 512-bit hashing for a version 5 CCP
device

Signed-off-by: Gary R Hook &lt;gary.hook@amd.com&gt;
Signed-off-by: Herbert Xu &lt;herbert@gondor.apana.org.au&gt;
</content>
</entry>
<entry>
<title>crypto: ccp - Assign DMA commands to the channel's CCP</title>
<updated>2017-03-16T09:43:08Z</updated>
<author>
<name>Gary R Hook</name>
<email>ghook@amd.com</email>
</author>
<published>2017-03-10T18:28:18Z</published>
<link rel='alternate' type='text/html' href='https://universe.0xinfinity.dev/distro/kernel/commit/?id=7c468447f40645fbf2a033dfdaa92b1957130d50'/>
<id>urn:sha1:7c468447f40645fbf2a033dfdaa92b1957130d50</id>
<content type='text'>
The CCP driver generally uses a round-robin approach when
assigning operations to available CCPs. For the DMA engine,
however, the DMA mappings of the SGs are associated with a
specific CCP. When an IOMMU is enabled, the IOMMU is
programmed based on this specific device.

If the DMA operations are not performed by that specific
CCP then addressing errors and I/O page faults will occur.

Update the CCP driver to allow a specific CCP device to be
requested for an operation and use this in the DMA engine
support.

Cc: &lt;stable@vger.kernel.org&gt; # 4.9.x-
Signed-off-by: Gary R Hook &lt;gary.hook@amd.com&gt;
Signed-off-by: Herbert Xu &lt;herbert@gondor.apana.org.au&gt;
</content>
</entry>
</feed>
