<feed xmlns='http://www.w3.org/2005/Atom'>
<title>kernel/include/kvm/arm_pmu.h, branch linux-5.1.y</title>
<subtitle>Hosts the 0x221E linux distro kernel.</subtitle>
<id>https://universe.0xinfinity.dev/distro/kernel/atom?h=linux-5.1.y</id>
<link rel='self' href='https://universe.0xinfinity.dev/distro/kernel/atom?h=linux-5.1.y'/>
<link rel='alternate' type='text/html' href='https://universe.0xinfinity.dev/distro/kernel/'/>
<updated>2017-07-25T13:18:01Z</updated>
<entry>
<title>KVM: arm/arm64: PMU: Fix overflow interrupt injection</title>
<updated>2017-07-25T13:18:01Z</updated>
<author>
<name>Andrew Jones</name>
<email>drjones@redhat.com</email>
</author>
<published>2017-07-01T16:26:54Z</published>
<link rel='alternate' type='text/html' href='https://universe.0xinfinity.dev/distro/kernel/commit/?id=d9f89b4e9290e46cd9b273e9ad0bff0f93e86fae'/>
<id>urn:sha1:d9f89b4e9290e46cd9b273e9ad0bff0f93e86fae</id>
<content type='text'>
kvm_pmu_overflow_set() is called from perf's interrupt handler,
making the call of kvm_vgic_inject_irq() from it introduced with
"KVM: arm/arm64: PMU: remove request-less vcpu kick" a really bad
idea, as it's quite easy to try and retake a lock that the
interrupted context is already holding. The fix is to use a vcpu
kick, leaving the interrupt injection to kvm_pmu_sync_hwstate(),
like it was doing before the refactoring. We don't just revert,
though, because before the kick was request-less, leaving the vcpu
exposed to the request-less vcpu kick race, and also because the
kick was used unnecessarily from register access handlers.

Reviewed-by: Christoffer Dall &lt;cdall@linaro.org&gt;
Signed-off-by: Andrew Jones &lt;drjones@redhat.com&gt;
Signed-off-by: Marc Zyngier &lt;marc.zyngier@arm.com&gt;
</content>
</entry>
<entry>
<title>KVM: arm64: Allow creating the PMU without the in-kernel GIC</title>
<updated>2017-06-08T14:59:44Z</updated>
<author>
<name>Christoffer Dall</name>
<email>cdall@linaro.org</email>
</author>
<published>2017-05-02T11:41:02Z</published>
<link rel='alternate' type='text/html' href='https://universe.0xinfinity.dev/distro/kernel/commit/?id=a2befacf50940017e0de8461c4b924a929c4edc5'/>
<id>urn:sha1:a2befacf50940017e0de8461c4b924a929c4edc5</id>
<content type='text'>
Since we got support for devices in userspace which allows reporting the
PMU overflow output status to userspace, we should actually allow
creating the PMU on systems without an in-kernel irqchip, which in turn
requires us to slightly clarify error codes for the ABI and move things
around for the initialization phase.

Signed-off-by: Christoffer Dall &lt;cdall@linaro.org&gt;
Reviewed-by: Marc Zyngier &lt;marc.zyngier@arm.com&gt;
</content>
</entry>
<entry>
<title>KVM: arm/arm64: Report PMU overflow interrupts to userspace irqchip</title>
<updated>2017-04-09T14:49:39Z</updated>
<author>
<name>Christoffer Dall</name>
<email>christoffer.dall@linaro.org</email>
</author>
<published>2017-02-01T11:51:52Z</published>
<link rel='alternate' type='text/html' href='https://universe.0xinfinity.dev/distro/kernel/commit/?id=3dbbdf78636e66094d82c4df496c54ff6ae46e31'/>
<id>urn:sha1:3dbbdf78636e66094d82c4df496c54ff6ae46e31</id>
<content type='text'>
When not using an in-kernel VGIC, but instead emulating an interrupt
controller in userspace, we should report the PMU overflow status to
that userspace interrupt controller using the KVM_CAP_ARM_USER_IRQ
feature.

Reviewed-by: Alexander Graf &lt;agraf@suse.de&gt;
Reviewed-by: Marc Zyngier &lt;marc.zyngier@arm.com&gt;
Signed-off-by: Christoffer Dall &lt;christoffer.dall@linaro.org&gt;
</content>
</entry>
<entry>
<title>arm64: KVM: fix build with CONFIG_ARM_PMU disabled</title>
<updated>2016-06-27T10:55:51Z</updated>
<author>
<name>Sudeep Holla</name>
<email>sudeep.holla@arm.com</email>
</author>
<published>2016-06-08T10:38:55Z</published>
<link rel='alternate' type='text/html' href='https://universe.0xinfinity.dev/distro/kernel/commit/?id=0efce9da1255f13d910842b62cb14371044a3c50'/>
<id>urn:sha1:0efce9da1255f13d910842b62cb14371044a3c50</id>
<content type='text'>
When CONFIG_ARM_PMU is disabled, we get the following build error:

arch/arm64/kvm/sys_regs.c: In function 'pmu_counter_idx_valid':
arch/arm64/kvm/sys_regs.c:564:27: error: 'ARMV8_PMU_CYCLE_IDX' undeclared (first use in this function)
  if (idx &gt;= val &amp;&amp; idx != ARMV8_PMU_CYCLE_IDX)
                           ^
arch/arm64/kvm/sys_regs.c:564:27: note: each undeclared identifier is reported only once for each function it appears in
arch/arm64/kvm/sys_regs.c: In function 'access_pmu_evcntr':
arch/arm64/kvm/sys_regs.c:592:10: error: 'ARMV8_PMU_CYCLE_IDX' undeclared (first use in this function)
    idx = ARMV8_PMU_CYCLE_IDX;
          ^
arch/arm64/kvm/sys_regs.c: In function 'access_pmu_evtyper':
arch/arm64/kvm/sys_regs.c:638:14: error: 'ARMV8_PMU_CYCLE_IDX' undeclared (first use in this function)
   if (idx == ARMV8_PMU_CYCLE_IDX)
              ^
arch/arm64/kvm/hyp/switch.c:86:15: error: 'ARMV8_PMU_USERENR_MASK' undeclared (first use in this function)
  write_sysreg(ARMV8_PMU_USERENR_MASK, pmuserenr_el0);

This patch fixes the build with CONFIG_ARM_PMU disabled.

Cc: Christoffer Dall &lt;christoffer.dall@linaro.org&gt;
Cc: Marc Zyngier &lt;marc.zyngier@arm.com&gt;
Signed-off-by: Sudeep Holla &lt;sudeep.holla@arm.com&gt;
Signed-off-by: Christoffer Dall &lt;christoffer.dall@linaro.org&gt;
</content>
</entry>
<entry>
<title>arm64: KVM: Add a new vcpu device control group for PMUv3</title>
<updated>2016-02-29T18:34:21Z</updated>
<author>
<name>Shannon Zhao</name>
<email>shannon.zhao@linaro.org</email>
</author>
<published>2016-01-11T13:35:32Z</published>
<link rel='alternate' type='text/html' href='https://universe.0xinfinity.dev/distro/kernel/commit/?id=bb0c70bcca6ba3c84afc2da7426f3b923bbe6825'/>
<id>urn:sha1:bb0c70bcca6ba3c84afc2da7426f3b923bbe6825</id>
<content type='text'>
To configure the virtual PMUv3 overflow interrupt number, we use the
vcpu kvm_device ioctl, encapsulating the KVM_ARM_VCPU_PMU_V3_IRQ
attribute within the KVM_ARM_VCPU_PMU_V3_CTRL group.

After configuring the PMUv3, call the vcpu ioctl with attribute
KVM_ARM_VCPU_PMU_V3_INIT to initialize the PMUv3.

Signed-off-by: Shannon Zhao &lt;shannon.zhao@linaro.org&gt;
Acked-by: Peter Maydell &lt;peter.maydell@linaro.org&gt;
Reviewed-by: Andrew Jones &lt;drjones@redhat.com&gt;
Reviewed-by: Christoffer Dall &lt;christoffer.dall@linaro.org&gt;
Signed-off-by: Marc Zyngier &lt;marc.zyngier@arm.com&gt;
</content>
</entry>
<entry>
<title>arm64: KVM: Add a new feature bit for PMUv3</title>
<updated>2016-02-29T18:34:21Z</updated>
<author>
<name>Shannon Zhao</name>
<email>shannon.zhao@linaro.org</email>
</author>
<published>2016-01-11T14:46:15Z</published>
<link rel='alternate' type='text/html' href='https://universe.0xinfinity.dev/distro/kernel/commit/?id=808e738142e7086ef793ebf9797099c392894e65'/>
<id>urn:sha1:808e738142e7086ef793ebf9797099c392894e65</id>
<content type='text'>
To support guest PMUv3, use one bit of the VCPU INIT feature array.
Initialize the PMU when initialzing the vcpu with that bit and PMU
overflow interrupt set.

Signed-off-by: Shannon Zhao &lt;shannon.zhao@linaro.org&gt;
Acked-by: Peter Maydell &lt;peter.maydell@linaro.org&gt;
Reviewed-by: Andrew Jones &lt;drjones@redhat.com&gt;
Signed-off-by: Marc Zyngier &lt;marc.zyngier@arm.com&gt;
</content>
</entry>
<entry>
<title>arm64: KVM: Free perf event of PMU when destroying vcpu</title>
<updated>2016-02-29T18:34:21Z</updated>
<author>
<name>Shannon Zhao</name>
<email>shannon.zhao@linaro.org</email>
</author>
<published>2015-09-11T07:18:05Z</published>
<link rel='alternate' type='text/html' href='https://universe.0xinfinity.dev/distro/kernel/commit/?id=5f0a714a2b63c25ffba5d832773f3ca4f0d02e21'/>
<id>urn:sha1:5f0a714a2b63c25ffba5d832773f3ca4f0d02e21</id>
<content type='text'>
When KVM frees VCPU, it needs to free the perf_event of PMU.

Signed-off-by: Shannon Zhao &lt;shannon.zhao@linaro.org&gt;
Reviewed-by: Marc Zyngier &lt;marc.zyngier@arm.com&gt;
Reviewed-by: Andrew Jones &lt;drjones@redhat.com&gt;
Signed-off-by: Marc Zyngier &lt;marc.zyngier@arm.com&gt;
</content>
</entry>
<entry>
<title>arm64: KVM: Reset PMU state when resetting vcpu</title>
<updated>2016-02-29T18:34:21Z</updated>
<author>
<name>Shannon Zhao</name>
<email>shannon.zhao@linaro.org</email>
</author>
<published>2015-09-11T03:30:22Z</published>
<link rel='alternate' type='text/html' href='https://universe.0xinfinity.dev/distro/kernel/commit/?id=2aa36e9840d71710f06b3c29634f044fde8bcbe5'/>
<id>urn:sha1:2aa36e9840d71710f06b3c29634f044fde8bcbe5</id>
<content type='text'>
When resetting vcpu, it needs to reset the PMU state to initial status.

Signed-off-by: Shannon Zhao &lt;shannon.zhao@linaro.org&gt;
Reviewed-by: Marc Zyngier &lt;marc.zyngier@arm.com&gt;
Reviewed-by: Andrew Jones &lt;drjones@redhat.com&gt;
Signed-off-by: Marc Zyngier &lt;marc.zyngier@arm.com&gt;
</content>
</entry>
<entry>
<title>arm64: KVM: Add PMU overflow interrupt routing</title>
<updated>2016-02-29T18:34:21Z</updated>
<author>
<name>Shannon Zhao</name>
<email>shannon.zhao@linaro.org</email>
</author>
<published>2016-02-26T11:29:19Z</published>
<link rel='alternate' type='text/html' href='https://universe.0xinfinity.dev/distro/kernel/commit/?id=b02386eb7dac7555a208d81aef2a0e5c6f0f8085'/>
<id>urn:sha1:b02386eb7dac7555a208d81aef2a0e5c6f0f8085</id>
<content type='text'>
When calling perf_event_create_kernel_counter to create perf_event,
assign a overflow handler. Then when the perf event overflows, set the
corresponding bit of guest PMOVSSET register. If this counter is enabled
and its interrupt is enabled as well, kick the vcpu to sync the
interrupt.

On VM entry, if there is counter overflowed and interrupt level is
changed, inject the interrupt with corresponding level. On VM exit, sync
the interrupt level as well if it has been changed.

Signed-off-by: Shannon Zhao &lt;shannon.zhao@linaro.org&gt;
Reviewed-by: Marc Zyngier &lt;marc.zyngier@arm.com&gt;
Reviewed-by: Andrew Jones &lt;drjones@redhat.com&gt;
Reviewed-by: Christoffer Dall &lt;christoffer.dall@linaro.org&gt;
Signed-off-by: Marc Zyngier &lt;marc.zyngier@arm.com&gt;
</content>
</entry>
<entry>
<title>arm64: KVM: Add helper to handle PMCR register bits</title>
<updated>2016-02-29T18:34:21Z</updated>
<author>
<name>Shannon Zhao</name>
<email>shannon.zhao@linaro.org</email>
</author>
<published>2015-10-28T04:10:30Z</published>
<link rel='alternate' type='text/html' href='https://universe.0xinfinity.dev/distro/kernel/commit/?id=76993739cd6f5b42e881fe3332b9f8eb98cd6907'/>
<id>urn:sha1:76993739cd6f5b42e881fe3332b9f8eb98cd6907</id>
<content type='text'>
According to ARMv8 spec, when writing 1 to PMCR.E, all counters are
enabled by PMCNTENSET, while writing 0 to PMCR.E, all counters are
disabled. When writing 1 to PMCR.P, reset all event counters, not
including PMCCNTR, to zero. When writing 1 to PMCR.C, reset PMCCNTR to
zero.

Signed-off-by: Shannon Zhao &lt;shannon.zhao@linaro.org&gt;
Reviewed-by: Marc Zyngier &lt;marc.zyngier@arm.com&gt;
Signed-off-by: Marc Zyngier &lt;marc.zyngier@arm.com&gt;
</content>
</entry>
</feed>
