Hosts the 0x221E linux distro kernel. https://universe.0xinfinity.dev/distro/kernel/atom?h=linux-5.1.y 2019-03-06T17:41:12Z 2019-03-06T17:41:12Z Linus Torvalds torvalds@linux-foundation.org 2019-03-06T17:41:12Z urn:sha1:384d11fa0e2ca15a3e7e52db34a4e43bedf0dc70 Pull ARM SoC driver updates from Arnd Bergmann: "As usual, the drivers/tee and drivers/reset subsystems get merged here, with the expected set of smaller updates and some new hardware support. The tee subsystem now supports device drivers to be attached to a tee, the first example here is a random number driver with its implementation in the secure world. Three new power domain drivers get added for specific chip families: - Broadcom BCM283x chips (used in Raspberry Pi) - Qualcomm Snapdragon phone chips - Xilinx ZynqMP FPGA SoCs One new driver is added to talk to the BPMP firmware on NVIDIA Tegra210 Existing drivers are extended for new SoC variants from NXP, NVIDIA, Amlogic and Qualcomm" * tag 'armsoc-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (113 commits) tee: optee: update optee_msg.h and optee_smc.h to dual license tee: add cancellation support to client interface dpaa2-eth: configure the cache stashing amount on a queue soc: fsl: dpio: configure cache stashing destination soc: fsl: dpio: enable frame data cache stashing per software portal soc: fsl: guts: make fsl_guts_get_svr() static hwrng: make symbol 'optee_rng_id_table' static tee: optee: Fix unsigned comparison with less than zero hwrng: Fix unsigned comparison with less than zero tee: fix possible error pointer ctx dereferencing hwrng: optee: Initialize some structs using memset instead of braces tee: optee: Initialize some structs using memset instead of braces soc: fsl: dpio: fix memory leak of a struct qbman on error exit path clk: tegra: dfll: Make symbol 'tegra210_cpu_cvb_tables' static soc: qcom: llcc-slice: Fix typos qcom: soc: llcc-slice: Consolidate some code qcom: soc: llcc-slice: Clear the global drv_data pointer on error drivers: soc: xilinx: Add ZynqMP power domain driver firmware: xilinx: Add APIs to control node status/power dt-bindings: power: Add ZynqMP power domain bindings ... 2019-02-15T17:00:05Z Arnd Bergmann arnd@arndb.de 2019-02-15T16:58:41Z urn:sha1:405bcfff172db863b7c4b63e0e0ef8508966c90a Qualcomm ARM Based Driver Updates for v5.1 * Add Qualcomm RPMh power domain driver and related changes * Fix issues with sleep/wake sets and batch API in RPMh * Update MAINTAINERS Qualcomm entry * Fixup RMTFS-mem sysfs and uevents * Fix error handling in GSBI * Add SMD-RPM compatible entry for SDM660 * tag 'qcom-drivers-for-5.1' of git://git.kernel.org/pub/scm/linux/kernel/git/agross/linux: soc: qcom: smd-rpm: Add sdm660 compatible soc: qcom: gsbi: Fix error handling in gsbi_probe() soc: qcom: rpmh: Avoid accessing freed memory from batch API drivers: qcom: rpmh: avoid sending sleep/wake sets immediately soc: qcom: rmtfs-mem: Make sysfs attributes world-readable soc: qcom: rmtfs-mem: Add class to enable uevents soc: qcom: update config dependencies for QCOM_RPMPD soc: qcom: rpmpd: Drop family A RPM dependency MAINTAINERS: update list of qcom drivers soc: qcom: rpmhpd: Mark mx as a parent for cx soc: qcom: rpmhpd: Add RPMh power domain driver soc: qcom: rpmpd: Add support for get/set performance state soc: qcom: rpmpd: Add a Power domain driver to model corners dt-bindings: power: Add qcom rpm power domain driver bindings OPP: Add support for parsing the 'opp-level' property dt-bindings: opp: Introduce opp-level bindings Signed-off-by: Arnd Bergmann <arnd@arndb.de> 2019-02-12T12:36:26Z Rajan Vaja rajan.vaja@xilinx.com 2019-02-01T22:08:48Z urn:sha1:8fd27fb4cf76a64d4ea4814b358541477dc7a31e Add documentation to describe ZynqMP power domain bindings. Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com> Signed-off-by: Jolly Shah <jolly.shah@xilinx.com> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Michal Simek <michal.simek@xilinx.com> 2019-02-07T15:34:46Z Weiyi Lu weiyi.lu@mediatek.com 2019-02-01T08:30:13Z urn:sha1:cd10b9343d1fd092cbf5fc3c2062942618158891 fix incorrect IC name that will affect the MT8183 power dt-bindings Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com> 2019-01-22T21:06:12Z Rajendra Nayak rnayak@codeaurora.org 2019-01-10T04:02:03Z urn:sha1:c6e6eff4d48f8b7180f9f94f1615ffe345fd7e5c Add DT bindings to describe the rpm/rpmh power domains found on Qualcomm Technologies, Inc. SoCs. These power domains communicate a performance state to RPM/RPMh, which then translates it into corresponding voltage on a PMIC rail. Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org> Reviewed-by: Stephen Boyd <swboyd@chromium.org> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org> Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Andy Gross <andy.gross@linaro.org> 2018-12-12T21:33:06Z Olof Johansson olof@lixom.net 2018-12-12T21:33:06Z urn:sha1:e3154317a063051a66231d43736276b5e3402f83 i.MX drivers change for 4.21: - A series from Aisheng that improves SCU power domain bindings by defining '#power-domain-cells' as 1, and adds i.MX8 SCU power domain driver support on top of it. - A series from Lucas that updates gpcv2 driver for scalability and adds i.MX8MQ support into the driver. - Increase gpc driver GPC_CLK_MAX definition to 7, as DISPLAY power domain on imx6sx has 7 clocks. * tag 'imx-drivers-4.21' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux: soc: imx: gpc: Increase GPC_CLK_MAX to 7 soc: imx: gpcv2: add support for i.MX8MQ SoC soc: imx: gpcv2: move register access table to domain data soc: imx: gpcv2: prefix i.MX7 specific defines firmware: imx: add SCU power domain driver firmware: imx: add pm svc headfile dt-bindings: fsl: scu: update power domain binding firmware: imx: remove resource id enums dt-bindings: imx: add scu resource id headfile Signed-off-by: Olof Johansson <olof@lixom.net> 2018-12-12T21:27:40Z Olof Johansson olof@lixom.net 2018-12-12T21:27:40Z urn:sha1:48ff08dd9aa9353ece8f5bebd217e824f1c6098c Renesas ARM Based SoC Drivers Updates for v4.21 SYSC Driver: * Common - Fix power domain control after system resume - Merge PM Domain registration and linking - Remove rcar_sysc_power_{down,up}() helpers * R-Car E3 (r8a77990) SoC - Fix initialization order of 3DG-{A,B} * R-Car V3H (r8a77980) SoC - Correct A3VIP[012] power domain hierarchy - Correct names of A2DP[01] power domains * R-Car V3M (r8a77970) SoC - Correct names of A2DP/A2CN power domains - emove non-existent CR7 power domain * R-Car M3-N (r8a77965) SoC - Remove non-existent A3IR power domain * tag 'renesas-drivers-for-v4.21' of https://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas: soc: renesas: rcar-sysc: Fix power domain control after system resume soc: renesas: rcar-sysc: Merge PM Domain registration and linking soc: renesas: rcar-sysc: Remove rcar_sysc_power_{down,up}() helpers soc: renesas: r8a77990-sysc: Fix initialization order of 3DG-{A,B} soc: renesas: r8a77980-sysc: Correct A3VIP[012] power domain hierarchy soc: renesas: r8a77980-sysc: Correct names of A2DP[01] power domains soc: renesas: r8a77970-sysc: Correct names of A2DP/A2CN power domains soc: renesas: r8a77970-sysc: Remove non-existent CR7 power domain soc: renesas: r8a77965-sysc: Remove non-existent A3IR power domain Signed-off-by: Olof Johansson <olof@lixom.net> 2018-12-05T00:50:36Z Lucas Stach l.stach@pengutronix.de 2018-11-16T15:49:27Z urn:sha1:685efffe37c921cf1d56dd3c8617dc67bc343a99 The GPCv2 on the Freescale i.MX8MQ SoC works in the same way as the GPCv2 on the i.MX7, but only controls more power domains with a different mapping. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Shawn Guo <shawnguo@kernel.org> 2018-12-03T21:06:27Z Olof Johansson olof@lixom.net 2018-12-03T21:06:27Z urn:sha1:e5734bebed406cc35875044b6af9bd67c6160680 This pull request contains Broadcom ARM/ARM64/MIPS SoCs drivers changes for 4.21, please pull the following changes: - James fixes the firmware interface after a commit changed the use of VLA and broke large transfers - Stefan adds a timeout check for Raspberry Pi firmware transactions and updates a bunch of SoC/firmware files to use SPDX tags - Wolfram switches the GISB bus arbiter to use dev_get_drvdata() - Yangtao provides a fix for a reference leak due to a call to of_find_node_by_path() - Florian fixes the CPU re-entry point out of S3 suspend with kernels built in Thumb2 mode * tag 'arm-soc/for-4.21/drivers' of https://github.com/Broadcom/stblinux: soc: bcm: brcmstb: Don't leak device tree node reference firmware: raspberrypi: Switch to SPDX identifier firmware: raspberrypi: Fix firmware calls with large buffers soc: bcm: Switch raspberrypi-power to SPDX identifier firmware: raspberrypi: Define timeout for transactions bus: brcmstb_gisb: simplify getting .driver_data soc: bcm: brcmstb: Fix re-entry point with a THUMB2_KERNEL Signed-off-by: Olof Johansson <olof@lixom.net> 2018-11-30T10:22:30Z Geert Uytterhoeven geert+renesas@glider.be 2018-11-29T10:56:18Z urn:sha1:160bfa7c724b348a90a12dd9694f351927a15b8e The R-Car Gen3 HardWare Manual Errata for Rev. 0.80 (Feb 28, 2018) renamed the A3VIP power domain on R-Car V3H to A3VIP0, and clarified the power domain hierarchy for the A3VIP[012] power domains. As the definition for the A3VIP0 domain is not yet used from DT, it can just be renamed. Fixes: 7755b40d07a8dba7 ("dt-bindings: power: add R8A77980 SYSC power domain definitions") Fixes: 41d6d8bd8ae94ca9 ("soc: renesas: rcar-sysc: add R8A77980 support") Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>