<feed xmlns='http://www.w3.org/2005/Atom'>
<title>kernel/include/dt-bindings/memory/tegra234-mc.h, branch linux-rolling-stable</title>
<subtitle>Hosts the 0x221E linux distro kernel.</subtitle>
<id>https://universe.0xinfinity.dev/distro/kernel/atom?h=linux-rolling-stable</id>
<link rel='self' href='https://universe.0xinfinity.dev/distro/kernel/atom?h=linux-rolling-stable'/>
<link rel='alternate' type='text/html' href='https://universe.0xinfinity.dev/distro/kernel/'/>
<updated>2023-05-16T10:06:55Z</updated>
<entry>
<title>dt-bindings: tegra: Add ICC IDs for dummy memory clients</title>
<updated>2023-05-16T10:06:55Z</updated>
<author>
<name>Sumit Gupta</name>
<email>sumitg@nvidia.com</email>
</author>
<published>2023-05-11T17:32:07Z</published>
<link rel='alternate' type='text/html' href='https://universe.0xinfinity.dev/distro/kernel/commit/?id=b0dae3df0546a5968ef8ea5b396d3de9b3a2295a'/>
<id>urn:sha1:b0dae3df0546a5968ef8ea5b396d3de9b3a2295a</id>
<content type='text'>
Add ICC IDs for dummy software clients representing CCPLEX clusters.

Signed-off-by: Sumit Gupta &lt;sumitg@nvidia.com&gt;
Acked-by: Krzysztof Kozlowski &lt;krzysztof.kozlowski@linaro.org&gt;
Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>dt-bindings: tegra: Update headers for Tegra234</title>
<updated>2022-11-21T12:27:17Z</updated>
<author>
<name>Jon Hunter</name>
<email>jonathanh@nvidia.com</email>
</author>
<published>2022-10-03T12:51:41Z</published>
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<id>urn:sha1:41155b6f6db8742c5f5247a141eca89c601c258c</id>
<content type='text'>
Update the device-tree clock, memory, power and reset headers for
Tegra234 by adding the definitions for all the various devices.

Signed-off-by: Jon Hunter &lt;jonathanh@nvidia.com&gt;
Acked-by: Rob Herring &lt;robh@kernel.org&gt;
Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>dt-bindings: Add headers for NVDEC on Tegra234</title>
<updated>2022-10-24T12:53:35Z</updated>
<author>
<name>Mikko Perttunen</name>
<email>mperttunen@nvidia.com</email>
</author>
<published>2022-09-20T08:11:57Z</published>
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<id>urn:sha1:0e2b014eeb257173c72014ebd02ab0d60643f0f8</id>
<content type='text'>
Add clock, memory controller, powergate and reset dt-binding headers
necessary for NVDEC.

Signed-off-by: Mikko Perttunen &lt;mperttunen@nvidia.com&gt;
Acked-by: Krzysztof Kozlowski &lt;krzysztof.kozlowski@linaro.org&gt;
Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>dt-bindings: Add Host1x context stream IDs on Tegra234</title>
<updated>2022-09-15T12:05:42Z</updated>
<author>
<name>Mikko Perttunen</name>
<email>mperttunen@nvidia.com</email>
</author>
<published>2022-09-07T08:38:43Z</published>
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<id>urn:sha1:cc99f95d49b3ee4617bb4154e32ae7ac14755fe2</id>
<content type='text'>
Add defines for stream IDs used for Host1x context isolation
on Tegra234. The same stream IDs are used for both NISO0 and
NISO1 SMMUs since Host1x's stream ID protection tables don't
make a distinction between the two.

Signed-off-by: Mikko Perttunen &lt;mperttunen@nvidia.com&gt;
Acked-by: Rob Herring &lt;robh@kernel.org&gt;
Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>dt-bindings: Add headers for Host1x and VIC on Tegra234</title>
<updated>2022-07-08T14:17:04Z</updated>
<author>
<name>Mikko Perttunen</name>
<email>mperttunen@nvidia.com</email>
</author>
<published>2022-06-27T14:19:57Z</published>
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<id>urn:sha1:63a6ef2360bdeffcdd41bcdd86937b6db17b573d</id>
<content type='text'>
Add clock, memory controller, powergate and reset dt-binding headers
for Host1x and VIC on Tegra234.

Signed-off-by: Mikko Perttunen &lt;mperttunen@nvidia.com&gt;
Acked-by: Krzysztof Kozlowski &lt;krzysztof.kozlowski@linaro.org&gt;
Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>dt-bindings: memory: Add Tegra234 MGBE memory clients</title>
<updated>2022-07-08T08:20:59Z</updated>
<author>
<name>Thierry Reding</name>
<email>treding@nvidia.com</email>
</author>
<published>2022-07-06T03:12:53Z</published>
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<id>urn:sha1:833f5a7eb2889067c45e5367aa7d5516df17520d</id>
<content type='text'>
Add the memory client and stream ID definitions for the MGBE hardware
found on Tegra234 SoCs.

Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
Signed-off-by: Bhadram Varka &lt;vbhadram@nvidia.com&gt;
Acked-by: Krzysztof Kozlowski &lt;krzysztof.kozlowski@linaro.org&gt;
Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>dt-bindings: Add headers for Tegra234 GPCDMA</title>
<updated>2022-06-08T13:50:24Z</updated>
<author>
<name>Akhil R</name>
<email>akhilrajeev@nvidia.com</email>
</author>
<published>2022-05-17T07:40:47Z</published>
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<id>urn:sha1:3ffb20f5c7891ab5bc61cb4044465d3ad1aebf49</id>
<content type='text'>
Add reset and IOMMU header for Tegra234 GPCDMA

Signed-off-by: Akhil R &lt;akhilrajeev@nvidia.com&gt;
Reviewed-by: Jon Hunter &lt;jonathanh@nvidia.com&gt;
Acked-by: Krzysztof Kozlowski &lt;krzysztof.kozlowski@linaro.org&gt;
Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>dt-bindings: memory: Add Tegra234 PCIe memory</title>
<updated>2022-02-24T19:00:25Z</updated>
<author>
<name>Vidya Sagar</name>
<email>vidyas@nvidia.com</email>
</author>
<published>2022-02-05T16:21:37Z</published>
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<id>urn:sha1:a4ad66da3fccebdcbd53d55c035d5851b73f8bcb</id>
<content type='text'>
Add the memory client and stream ID definitions for the PCIe hardware
found on Tegra234 SoCs.

Signed-off-by: Vidya Sagar &lt;vidyas@nvidia.com&gt;
Acked-by: Rob Herring &lt;robh@kernel.org&gt;
Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>dt-bindings: Add HDA support for Tegra234</title>
<updated>2022-02-24T17:34:33Z</updated>
<author>
<name>Mohan Kumar</name>
<email>mkumard@nvidia.com</email>
</author>
<published>2022-02-16T09:22:38Z</published>
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<id>urn:sha1:07d743902a1205d54d93c0637c22575811014431</id>
<content type='text'>
Add hda clocks, memory ,power and reset binding entries
for Tegra234.

Signed-off-by: Mohan Kumar &lt;mkumard@nvidia.com&gt;
Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>dt-bindings: Add Tegra234 APE support</title>
<updated>2022-02-17T14:21:43Z</updated>
<author>
<name>Sameer Pujar</name>
<email>spujar@nvidia.com</email>
</author>
<published>2022-01-27T07:27:32Z</published>
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<id>urn:sha1:40efe139ff605d80cc829ddf8c50c71d20399bf8</id>
<content type='text'>
Add clocks, power-domain and memory bindings to support APE subsystem
on Tegra234.

Signed-off-by: Sameer Pujar &lt;spujar@nvidia.com&gt;
Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
</feed>
