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<title>kernel/include/dt-bindings/memory/tegra186-mc.h, branch linux-5.11.y</title>
<subtitle>Hosts the 0x221E linux distro kernel.</subtitle>
<id>https://universe.0xinfinity.dev/distro/kernel/atom?h=linux-5.11.y</id>
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<updated>2020-01-09T18:10:04Z</updated>
<entry>
<title>dt-bindings: memory: Add Tegra186 memory client IDs</title>
<updated>2020-01-09T18:10:04Z</updated>
<author>
<name>Thierry Reding</name>
<email>treding@nvidia.com</email>
</author>
<published>2019-12-22T14:10:23Z</published>
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<id>urn:sha1:96b0239bbd6153b70c14c80664ebb43cd2ddacd9</id>
<content type='text'>
Add IDs for the memory clients found on NVIDIA Tegra186 SoCs. This will
be used to describe interconnect paths from devices to system memory.

Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
Acked-by: Rob Herring &lt;robh@kernel.org&gt;
</content>
</entry>
<entry>
<title>dt-bindings: memory: Add Tegra186 support</title>
<updated>2017-12-13T11:53:43Z</updated>
<author>
<name>Thierry Reding</name>
<email>treding@nvidia.com</email>
</author>
<published>2017-12-13T11:53:43Z</published>
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<id>urn:sha1:029ab5eaf091ce5eaa1f3017f66fd1d10f431d61</id>
<content type='text'>
As opposed to earlier incarnations, the memory controller on Tegra186 no
longer implements an SMMU. Instead the SMMU is a regular ARM SMMU and in
a separate IP block.

However, the memory controller programs the SMMU stream IDs for each of
the memory clients. Add a header file with definitions for each of these
stream IDs and mark the #iommu-cells property as required on Tegra30 to
Tegra210 in the device tree bindings.

Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
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