<feed xmlns='http://www.w3.org/2005/Atom'>
<title>kernel/include/dt-bindings/gpio, branch linux-5.11.y</title>
<subtitle>Hosts the 0x221E linux distro kernel.</subtitle>
<id>https://universe.0xinfinity.dev/distro/kernel/atom?h=linux-5.11.y</id>
<link rel='self' href='https://universe.0xinfinity.dev/distro/kernel/atom?h=linux-5.11.y'/>
<link rel='alternate' type='text/html' href='https://universe.0xinfinity.dev/distro/kernel/'/>
<updated>2020-12-05T21:40:28Z</updated>
<entry>
<title>dt-bindings: gpio: Add a binding header for the MSC313 GPIO driver</title>
<updated>2020-12-05T21:40:28Z</updated>
<author>
<name>Daniel Palmer</name>
<email>daniel@0x0f.com</email>
</author>
<published>2020-11-29T11:07:58Z</published>
<link rel='alternate' type='text/html' href='https://universe.0xinfinity.dev/distro/kernel/commit/?id=588cc1a02633dcc9ee0923d052cd20087e1a6b0a'/>
<id>urn:sha1:588cc1a02633dcc9ee0923d052cd20087e1a6b0a</id>
<content type='text'>
Header adds defines for the gpio number of each pad from the driver view.

The gpio block seems to have enough registers for 128 lines but what line
is mapped to a physical pin depends on the chip. The gpio block also seems
to contain some registers that are not related to gpio but needed somewhere
to go.

Because of the above the driver itself uses the index of a pin's offset in
an array of the possible offsets for a chip as the gpio number.

Signed-off-by: Daniel Palmer &lt;daniel@0x0f.com&gt;
Reviewed-by: Rob Herring &lt;robh@kernel.org&gt;
Link: https://lore.kernel.org/r/20201129110803.2461700-2-daniel@0x0f.com
Signed-off-by: Linus Walleij &lt;linus.walleij@linaro.org&gt;
</content>
</entry>
<entry>
<title>dt-bindings: gpio: Use Tegra186-specific include guard</title>
<updated>2020-12-05T21:34:12Z</updated>
<author>
<name>Thierry Reding</name>
<email>treding@nvidia.com</email>
</author>
<published>2020-11-27T14:08:51Z</published>
<link rel='alternate' type='text/html' href='https://universe.0xinfinity.dev/distro/kernel/commit/?id=64a38367b45015de42521c4835541f43838caf39'/>
<id>urn:sha1:64a38367b45015de42521c4835541f43838caf39</id>
<content type='text'>
Use a unique include guard for the Tegra186 GPIO DT bindings header to
avoid clashes with the DT bindings header for earlier chips.

Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
Link: https://lore.kernel.org/r/20201127140852.123192-2-thierry.reding@gmail.com
Signed-off-by: Linus Walleij &lt;linus.walleij@linaro.org&gt;
</content>
</entry>
<entry>
<title>pinctrl: add compatible for Amlogic Meson A1 pin controller</title>
<updated>2019-11-04T15:31:34Z</updated>
<author>
<name>Qianggui Song</name>
<email>qianggui.song@amlogic.com</email>
</author>
<published>2019-10-25T11:49:24Z</published>
<link rel='alternate' type='text/html' href='https://universe.0xinfinity.dev/distro/kernel/commit/?id=26f6a7524dd3366eff8cb0e733a856e8d84c6f68'/>
<id>urn:sha1:26f6a7524dd3366eff8cb0e733a856e8d84c6f68</id>
<content type='text'>
Add new compatible name for Amlogic's Meson-A1 pin controller
add a dt-binding header file which document the detail pin names.
Note that A1 doesn't need DS bank reg any more, use gpio reg as
base.

Reviewed-by: Rob Herring &lt;robh@kernel.org&gt;
Reviewed-by: Neil Armstrong &lt;narmstrong@baylibre.com&gt;
Signed-off-by: Qianggui Song &lt;qianggui.song@amlogic.com&gt;
Link: https://lore.kernel.org/r/1572004167-24150-2-git-send-email-qianggui.song@amlogic.com
Signed-off-by: Linus Walleij &lt;linus.walleij@linaro.org&gt;
</content>
</entry>
<entry>
<title>Merge tag 'tegra-for-5.3-arm64-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into arm/dt</title>
<updated>2019-06-25T11:48:32Z</updated>
<author>
<name>Olof Johansson</name>
<email>olof@lixom.net</email>
</author>
<published>2019-06-25T11:48:32Z</published>
<link rel='alternate' type='text/html' href='https://universe.0xinfinity.dev/distro/kernel/commit/?id=9c644f83ea6ee4b6f9caeb01bdfac9f88ec30892'/>
<id>urn:sha1:9c644f83ea6ee4b6f9caeb01bdfac9f88ec30892</id>
<content type='text'>
arm64: tegra: Device tree changes for v5.3-rc1

This contains the bulk of the Tegra changes this cycle. It has a bunch
of improvements across almost all boards. These are mostly small and not
too exciting additions.

Most notably perhaps is the continuation of Jetson Nano support, which
is now mostly on feature parity with Jetson TX1.

* tag 'tegra-for-5.3-arm64-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux: (28 commits)
  arm64: tegra: Enable PCIe slots in P2972-0000 board
  arm64: tegra: Add P2U and PCIe controller nodes to Tegra194 DT
  arm64: tegra: Add PEX DPD states as pinctrl properties
  arm64: tegra: Enable ACONNECT, ADMA and AGIC
  arm64: tegra: Add ACONNECT, ADMA and AGIC nodes
  arm64: tegra: Sort device tree nodes alphabetically
  arm64: tegra: Fix Jetson Nano GPU regulator
  arm64: tegra: Update Jetson TX1 GPU regulator timings
  arm64: tegra: Fix AGIC register range
  arm64: tegra: Add INA3221 channel info for Jetson TX2
  arm64: tegra: Enable PWM on Jetson Nano
  arm64: tegra: Enable CPU sleep on Jetson Nano
  arm64: tegra: Add ID EEPROMs on Jetson Nano
  arm64: tegra: Add ID EEPROM for Jetson TX2 Developer Kit
  arm64: tegra: Add ID EEPROM for Jetson TX2 module
  arm64: tegra: Add ID EEPROM for Jetson TX1 Developer Kit
  arm64: tegra: Add ID EEPROM for Jetson TX1 module
  arm64: tegra: Don't use architected timer for suspend on Tegra210
  arm64: tegra: Mark architected timer as always on
  arm64: tegra: Add pin control states for I2C on Tegra186
  ...

Signed-off-by: Olof Johansson &lt;olof@lixom.net&gt;
</content>
</entry>
<entry>
<title>treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 446</title>
<updated>2019-06-05T15:37:18Z</updated>
<author>
<name>Thomas Gleixner</name>
<email>tglx@linutronix.de</email>
</author>
<published>2019-06-01T08:09:00Z</published>
<link rel='alternate' type='text/html' href='https://universe.0xinfinity.dev/distro/kernel/commit/?id=3c910ecbdda4227abd145967774f92b1a3341493'/>
<id>urn:sha1:3c910ecbdda4227abd145967774f92b1a3341493</id>
<content type='text'>
Based on 1 normalized pattern(s):

  this program is free software you can redistribute it and or modify
  it under the terms of the gnu general public license version 2 as
  published by the free software foundation you should have received a
  copy of the gnu general public license along with this program if
  not see http www gnu org licenses

extracted by the scancode license scanner the SPDX license identifier

  GPL-2.0-only

has been chosen to replace the boilerplate/reference in 30 file(s).

Signed-off-by: Thomas Gleixner &lt;tglx@linutronix.de&gt;
Reviewed-by: Allison Randal &lt;allison@lohutok.net&gt;
Cc: linux-spdx@vger.kernel.org
Link: https://lkml.kernel.org/r/20190531190115.962665879@linutronix.de
Signed-off-by: Greg Kroah-Hartman &lt;gregkh@linuxfoundation.org&gt;
</content>
</entry>
<entry>
<title>dt-bindings: tegra186-gpio: Remove unused definitions</title>
<updated>2019-05-21T14:32:10Z</updated>
<author>
<name>Thierry Reding</name>
<email>treding@nvidia.com</email>
</author>
<published>2018-09-19T17:12:14Z</published>
<link rel='alternate' type='text/html' href='https://universe.0xinfinity.dev/distro/kernel/commit/?id=8d9a8543be03096eb6d25663f33f3183bd62b3a6'/>
<id>urn:sha1:8d9a8543be03096eb6d25663f33f3183bd62b3a6</id>
<content type='text'>
Now that all users of the old definitions have been updated to use the
Tegra186 specific prefix, remove the unused definitions.

Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>dt-bindings: gpio: document the new pull-up/pull-down flags</title>
<updated>2019-02-13T08:07:43Z</updated>
<author>
<name>Thomas Petazzoni</name>
<email>thomas.petazzoni@bootlin.com</email>
</author>
<published>2019-02-07T16:28:55Z</published>
<link rel='alternate' type='text/html' href='https://universe.0xinfinity.dev/distro/kernel/commit/?id=ede033e1e863c36729de25b57145fff287415830'/>
<id>urn:sha1:ede033e1e863c36729de25b57145fff287415830</id>
<content type='text'>
This commit extends the flags that can be used in GPIO specifiers to
indicate if a pull-up resistor or pull-down resistor should be
enabled.

While some pinctrl DT bindings already offer the capability of
configuring pull-up/pull-down resistors at the pin level, a number of
simple GPIO controllers don't have any pinmuxing capability, and
therefore do not rely on the pinctrl DT bindings.

Such simple GPIO controllers however sometimes allow to configure
pull-up and pull-down resistors on a per-pin basis, and whether such
resistors should be enabled or not is a highly board-specific HW
characteristic.

By using two additional bits of the GPIO flag specifier, we can easily
allow the Device Tree to describe which GPIOs should have their
pull-up or pull-down resistors enabled. Even though the two options
are mutually exclusive, we still need two bits to encode at least
three states: no pull-up/pull-down, pull-up, pull-down.

Signed-off-by: Thomas Petazzoni &lt;thomas.petazzoni@bootlin.com&gt;
Signed-off-by: Linus Walleij &lt;linus.walleij@linaro.org&gt;
</content>
</entry>
<entry>
<title>dt-bindings: tegra186-gpio: Add Tegra186 specific prefix</title>
<updated>2018-12-07T10:07:12Z</updated>
<author>
<name>Thierry Reding</name>
<email>treding@nvidia.com</email>
</author>
<published>2018-11-23T12:43:41Z</published>
<link rel='alternate' type='text/html' href='https://universe.0xinfinity.dev/distro/kernel/commit/?id=25fbc9e8d3673d372ad6ae44a8d4f850879f50ad'/>
<id>urn:sha1:25fbc9e8d3673d372ad6ae44a8d4f850879f50ad</id>
<content type='text'>
Subsequent generations of Tegra, such as Tegra194, contain a completely
different set of GPIOs. In order to clarify that the Tegra186 defines
are indeed specific to Tegra186, change the prefix from TEGRA_ to
TEGRA186_.

Note that for now we need to keep the old definitions in place to avoid
breaking compilation in file that use this header. Once all users have
been converted to use the new defines, the old ones can be removed.

Also note that this is only a naming change and doesn't affect device
tree ABI.

Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
Acked-by: Jon Hunter &lt;jonathanh@nvidia.com
Signed-off-by: Linus Walleij &lt;linus.walleij@linaro.org&gt;
</content>
</entry>
<entry>
<title>pinctrl: Add compatibles for Amlogic Meson G12A pin controllers</title>
<updated>2018-08-29T08:34:53Z</updated>
<author>
<name>Yixun Lan</name>
<email>yixun.lan@amlogic.com</email>
</author>
<published>2018-08-07T02:06:33Z</published>
<link rel='alternate' type='text/html' href='https://universe.0xinfinity.dev/distro/kernel/commit/?id=3cd3c83f675259aaf6bebdafb37622be2139fb8f'/>
<id>urn:sha1:3cd3c83f675259aaf6bebdafb37622be2139fb8f</id>
<content type='text'>
Add new compatible name for Amlogic's Meson-G12A pin controllers,
add a dt-binding header file which document the detail pin names.

Acked-by: Martin Blumenstingl &lt;martin.blumenstingl@googlemail.com&gt;
Reviewed-by: Rob Herring &lt;robh@kernel.org&gt;
Signed-off-by: Xingyu Chen &lt;xingyu.chen@amlogic.com&gt;
Signed-off-by: Yixun Lan &lt;yixun.lan@amlogic.com&gt;
Signed-off-by: Linus Walleij &lt;linus.walleij@linaro.org&gt;
</content>
</entry>
<entry>
<title>Merge tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc</title>
<updated>2018-04-06T04:18:09Z</updated>
<author>
<name>Linus Torvalds</name>
<email>torvalds@linux-foundation.org</email>
</author>
<published>2018-04-06T04:18:09Z</published>
<link rel='alternate' type='text/html' href='https://universe.0xinfinity.dev/distro/kernel/commit/?id=b240b419db5d624ce7a5a397d6f62a1a686009ec'/>
<id>urn:sha1:b240b419db5d624ce7a5a397d6f62a1a686009ec</id>
<content type='text'>
Pull ARM SoC device tree updates from Arnd Bergmann:
 "This is the usual set of changes for device trees, with over 700
  non-merged changesets. There is an ongoing set of dtc warning fixes
  and the usual bugfixes, cleanups and added device support.

  The most interesting bit as usual is support for new machines listed
  below:

   - The Allwinner H6 makes its debut with the Pine-H64 board, and we
     get two new machines based on its older siblings: the H5 based
     OrangePi Zero+ and the A64 based Teres-I Laptop from Olimex. On the
     32-bit side, we add The Olimex som204 based on Allwinner A20, and
     the Banana Pi M2 Zero development board (based on H2).

   - NVIDIA adds support for Tegra194 aka "Xavier", plus their p2972
     development board and p2888 CPU module.

   - The Nuvoton npcm750 is a BMC that was newly added, for now we only
     support running on the evaluation board.

   - STmicroelectronics stm32 gains support for the stm32mp157c and two
     evaluation boards.

   - The Toradex Colibri board family grows a few members based on the
     i.MX6ULL variant.

   - The Advantec DMS-BA16 is a Qseven module using the NXP i.MX6 family
     of chips.

   - The Phytec phyBOARD Mira is a family of industrial boards based on
     i.MX6. For now, four models get added.

   - TI am335x based PDU-001 is an industrial embedded machine used for
     traffic monitoring

   - The Aspeed platform now supports running on the BMC on the Qualcomm
     Centriq 2400 server

   - Samsung Exynos4 based Galaxy S3 is a family of mobile phones
     Qualcomm msm8974 based Galaxy S5 is a rather different phone made
     by the same company.

   - The Xilinx Zynq and ZynqMP platforms now gained a lot of dts file
     for the various boards made by Xilinx themselves, as well as the
     Digilent Zybo Z7.

   - The ARM Versatile family now supports the "IB2" interface board.

   - The Renesas H2 based "Stout" and the H3 based Salvator-X are more
     evaluation boards named after a kind of beer, as most of them are.
     The r8a77980 (V3H) based "Condor" apparently doesn't follow that
     tradition. ;-)

   - ROC-RK3328-CC is a simple developement board from the Libre
     Computer Project, based on the Rockchips RK3328 SoC

   - Haiku is another development board plus Qseven module based on
     Rockchips RK3368 and made by Theobroma Systems"

* tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (701 commits)
  arm: dts: modify Nuvoton NPCM7xx device tree structure
  arm: dts: modify Makefile NPCM750 configuration name
  arm: dts: modify clock binding in NPCM750 device tree
  arm: dts: modify timer register size in NPCM750 device tree
  arm: dts: modify UART compatible name in NPCM750 device tree
  arm: dts: add watchdog device to NPCM750 device tree
  arm64: dts: uniphier: add ethernet node for PXs3
  ARM: dts: uniphier: add pinctrl groups of ethernet for second instance
  arm: dts: kirkwood*.dts: use SPDX-License-Identifier for board using GPL-2.0+
  arm: dts: kirkwood*.dts: use SPDX-License-Identifier for boards using GPL-2.0+/MIT
  arm: dts: kirkwood*.dts: use SPDX-License-Identifier for boards using GPL-2.0
  arm: dts: armada-385-turris-omnia: use SPDX-License-Identifier
  arm: dts: armada-385-db-ap: use SPDX-License-Identifier
  arm: dts: armada-388-rd: use SPDX-License-Identifier
  arm: dts: armada-xp-db-xc3-24g4xg: use SPDX-License-Identifier
  arm: dts: armada-xp-db-dxbc2: use SPDX-License-Identifier
  arm: dts: armada-370-db: use SPDX-License-Identifier
  arm: dts: armada-*.dts: use SPDX-License-Identifier for most of the Armada based board
  arm: dts: armada-xp-98dx: use SPDX-License-Identifier for prestara 98d SoCs
  arm: dts: armada-*.dtsi: use SPDX-License-Identifier for most of the Armada SoCs
  ...
</content>
</entry>
</feed>
