kernel/include/dt-bindings/clock/vf610-clock.h, branch linux-5.11.y

clk: imx: vf610: Add CRC clock

2020-08-23T02:08:35Z

Add the clock for CRC block allowing it to be enabled by consumers. Signed-off-by: Krzysztof Kozlowski Signed-off-by: Shawn Guo

clk: imx: vf610: add CAAM clock

2020-06-23T07:10:05Z

According to Vybrid Security RM, CCM_CCGR11[CG176] can be used to gate CAAM ipg clock. Signed-off-by: Horia Geantă Signed-off-by: Andrey Smirnov Cc: Chris Healy Cc: Shawn Guo Cc: Fabio Estevam Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Cc: linux-imx@nxp.com Tested-by: Chris Healy Signed-off-by: Shawn Guo

treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 152

2019-05-30T18:26:32Z

Based on 1 normalized pattern(s): this program is free software you can redistribute it and or modify it under the terms of the gnu general public license as published by the free software foundation either version 2 of the license or at your option any later version extracted by the scancode license scanner the SPDX license identifier GPL-2.0-or-later has been chosen to replace the boilerplate/reference in 3029 file(s). Signed-off-by: Thomas Gleixner Reviewed-by: Allison Randal Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190527070032.746973796@linutronix.de Signed-off-by: Greg Kroah-Hartman

clk: imx: vf610: fix whitespace in vf610-clock.h

2016-04-12T01:31:08Z

There is whitespace in VF610_CLK_OCOTP line. Fix it. Signed-off-by: Shawn Guo

clk: imx: vf610: add TCON ipg clock

2016-04-12T01:22:17Z

Add the ipg (bus) clock for the TCON modules (Timing Controller). This module is required by the new DCU DRM driver, since the display signals pass through TCON. Signed-off-by: Stefan Agner Signed-off-by: Shawn Guo

clk: imx: vf610: add WKPU unit

2016-03-31T09:02:02Z

Signed-off-by: Stefan Agner Acked-by: Stephen Boyd Signed-off-by: Shawn Guo

clk: imx: vf610: leave DDR clock on

2016-03-31T09:01:58Z

To use STOP mode without putting DDR3 into self-refresh mode, we need to keep the DDR clock enabled. Use the new gate configuration with a value of 2 to make sure that the clock is enabled in RUN, WAIT and STOP mode. Signed-off-by: Stefan Agner Signed-off-by: Shawn Guo

clk: clk-vf610: Add clock for Vybrid OCOTP controller

2015-09-23T01:02:40Z

Add clock support for Vybrid On-Chip One Time Programmable (OCOTP) controller. While the OCOTP block does not require explicit clock gating, for programming the OCOTP timing register the clock rate of ipg clock is required for timing calculations related to fuse and shadow register read sequence. We explicitly specify the ipg clock for OCOTP as a result. Signed-off-by: Sanchayan Maity Signed-off-by: Shawn Guo

ARM: imx: clk-vf610: enable debug access port by default

2015-06-03T06:49:36Z

Enabled DAP (debug access port) by default. This enables the hw- breakpoint framework to make use of the breakpoints and watchpoints supported by hardware. [ 0.215805] hw-breakpoint: found 2 (+1 reserved) breakpoint and 1 watchpoint registers. [ 0.224624] hw-breakpoint: maximum watchpoint size is 4 bytes. Without this clock, the hw-breakpoint driver claims an undefined instruction during initialization: [ 0.227380] hw-breakpoint: Debug register access (0xee003e17) caused undefined instruction on CPU 0 [ 0.227519] hw-breakpoint: CPU 0 failed to disable vector catch Signed-off-by: Stefan Agner Signed-off-by: Shawn Guo

ARM: imx: clk-vf610: Add clock for SNVS

2015-01-13T11:16:26Z

Add support for clock gating of the SNVS peripheral. Signed-off-by: Sanchayan Maity Signed-off-by: Shawn Guo