kernel/include/dt-bindings/clock/vf610-clock.h, branch linux-4.15.y

clk: imx: vf610: fix whitespace in vf610-clock.h

2016-04-12T01:31:08Z

There is whitespace in VF610_CLK_OCOTP line. Fix it. Signed-off-by: Shawn Guo

clk: imx: vf610: add TCON ipg clock

2016-04-12T01:22:17Z

Add the ipg (bus) clock for the TCON modules (Timing Controller). This module is required by the new DCU DRM driver, since the display signals pass through TCON. Signed-off-by: Stefan Agner Signed-off-by: Shawn Guo

clk: imx: vf610: add WKPU unit

2016-03-31T09:02:02Z

Signed-off-by: Stefan Agner Acked-by: Stephen Boyd Signed-off-by: Shawn Guo

clk: imx: vf610: leave DDR clock on

2016-03-31T09:01:58Z

To use STOP mode without putting DDR3 into self-refresh mode, we need to keep the DDR clock enabled. Use the new gate configuration with a value of 2 to make sure that the clock is enabled in RUN, WAIT and STOP mode. Signed-off-by: Stefan Agner Signed-off-by: Shawn Guo

clk: clk-vf610: Add clock for Vybrid OCOTP controller

2015-09-23T01:02:40Z

Add clock support for Vybrid On-Chip One Time Programmable (OCOTP) controller. While the OCOTP block does not require explicit clock gating, for programming the OCOTP timing register the clock rate of ipg clock is required for timing calculations related to fuse and shadow register read sequence. We explicitly specify the ipg clock for OCOTP as a result. Signed-off-by: Sanchayan Maity Signed-off-by: Shawn Guo

ARM: imx: clk-vf610: enable debug access port by default

2015-06-03T06:49:36Z

Enabled DAP (debug access port) by default. This enables the hw- breakpoint framework to make use of the breakpoints and watchpoints supported by hardware. [ 0.215805] hw-breakpoint: found 2 (+1 reserved) breakpoint and 1 watchpoint registers. [ 0.224624] hw-breakpoint: maximum watchpoint size is 4 bytes. Without this clock, the hw-breakpoint driver claims an undefined instruction during initialization: [ 0.227380] hw-breakpoint: Debug register access (0xee003e17) caused undefined instruction on CPU 0 [ 0.227519] hw-breakpoint: CPU 0 failed to disable vector catch Signed-off-by: Stefan Agner Signed-off-by: Shawn Guo

ARM: imx: clk-vf610: Add clock for SNVS

2015-01-13T11:16:26Z

Add support for clock gating of the SNVS peripheral. Signed-off-by: Sanchayan Maity Signed-off-by: Shawn Guo

ARM: imx: clk-vf610: define PLL's clock tree

2014-11-04T05:40:14Z

So far, the required PLL's (PLL1/PLL2/PLL5) have been initialized by boot loader and the kernel code defined fixed rates according to those default configurations. Beginning with the USB PLL7 the code started to initialize the PLL's itself (using imx_clk_pllv3). However, since commit dc4805c2e78ba5a22ea1632f3e3e4ee601a1743b (ARM: imx: remove ENABLE and BYPASS bits from clk-pllv3 driver) imx_clk_pllv3 no longer takes care of the ENABLE and BYPASS bits, hence the USB PLL were not configured correctly anymore. This patch not only fixes those USB PLL's, but also makes use of the imx_clk_pllv3 for all PLL's and alignes the code with the PLL support of the i.MX6 series. Signed-off-by: Stefan Agner Signed-off-by: Shawn Guo

ARM: imx: clk-vf610: Add USBPHY clocks

2014-09-16T02:06:45Z

This commit adds PLL7 which is required for USBPHY1. It also adds the USB PHY and USB Controller clocks and the gates to enable them. Acked-by: Jingchang Lu Signed-off-by: Stefan Agner Signed-off-by: Shawn Guo

ARM: imx: clk-vf610: fix FlexCAN clock gating

2014-07-18T08:11:40Z

Extend the clock control for FlexCAN with the second gate which enable the clocks in the Clock Divider (CCM_CSCDR2) register too. Signed-off-by: Stefan Agner Signed-off-by: Shawn Guo