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<title>kernel/include/dt-bindings/clock/r8a7792-clock.h, branch linux-6.2.y</title>
<subtitle>Hosts the 0x221E linux distro kernel.</subtitle>
<id>https://universe.0xinfinity.dev/distro/kernel/atom?h=linux-6.2.y</id>
<link rel='self' href='https://universe.0xinfinity.dev/distro/kernel/atom?h=linux-6.2.y'/>
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<updated>2019-05-30T18:26:32Z</updated>
<entry>
<title>treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 152</title>
<updated>2019-05-30T18:26:32Z</updated>
<author>
<name>Thomas Gleixner</name>
<email>tglx@linutronix.de</email>
</author>
<published>2019-05-27T06:55:01Z</published>
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<id>urn:sha1:2874c5fd284268364ece81a7bd936f3c8168e567</id>
<content type='text'>
Based on 1 normalized pattern(s):

  this program is free software you can redistribute it and or modify
  it under the terms of the gnu general public license as published by
  the free software foundation either version 2 of the license or at
  your option any later version

extracted by the scancode license scanner the SPDX license identifier

  GPL-2.0-or-later

has been chosen to replace the boilerplate/reference in 3029 file(s).

Signed-off-by: Thomas Gleixner &lt;tglx@linutronix.de&gt;
Reviewed-by: Allison Randal &lt;allison@lohutok.net&gt;
Cc: linux-spdx@vger.kernel.org
Link: https://lkml.kernel.org/r/20190527070032.746973796@linutronix.de
Signed-off-by: Greg Kroah-Hartman &lt;gregkh@linuxfoundation.org&gt;
</content>
</entry>
<entry>
<title>ARM: dts: r8a7792: Correct Z clock</title>
<updated>2017-04-03T10:33:23Z</updated>
<author>
<name>Geert Uytterhoeven</name>
<email>geert+renesas@glider.be</email>
</author>
<published>2017-04-03T09:53:08Z</published>
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<id>urn:sha1:7b39e985cfc18bba43646240b10a830046382abf</id>
<content type='text'>
Unlike other R-Car Gen2 SoCs with Cortex-A15 CPU cores, R-Car V2H does
not have a programmable Z clock (Cortex-A15 CPU core clock), but uses a
fixed divider.
This is similar to the Z2 clock (Cortex-A7 CPU core clock) on R-Car E2.

Hence:
  - Remove the Z clock output from the cpg_clocks node, as this implied
    a programmable clock,
  - Add the Z clock as a fixed factor clock,
  - Let the first CPU node point to the new Z clock,
  - Remove the Z clock index from the bindings (this definition was used
    by r8a7792.dtsi only, and was not a contract between DT and driver).

Fixes: 7c4163aae3d8e5b9 ("ARM: dts: r8a7792: initial SoC device tree")
Signed-off-by: Geert Uytterhoeven &lt;geert+renesas@glider.be&gt;
Signed-off-by: Simon Horman &lt;horms+renesas@verge.net.au&gt;
</content>
</entry>
<entry>
<title>ARM: dts: r8a7792: Add INTC-SYS clock to device tree</title>
<updated>2017-03-10T09:20:25Z</updated>
<author>
<name>Geert Uytterhoeven</name>
<email>geert+renesas@glider.be</email>
</author>
<published>2017-03-06T16:58:09Z</published>
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<id>urn:sha1:90dce5428ae5499f06d91297ef10b3b613044774</id>
<content type='text'>
Link the ARM GIC to the INTC-SYS module clock, and add it to the "always
on" PM Domain, so it can be power managed using that clock.

Note that currently the GIC-400 driver doesn't support module clocks nor
Runtime PM, so this must be handled as a critical clock.

Signed-off-by: Geert Uytterhoeven &lt;geert+renesas@glider.be&gt;
Signed-off-by: Simon Horman &lt;horms+renesas@verge.net.au&gt;
</content>
</entry>
<entry>
<title>ARM: dts: r8a7792: remove ADSP clock</title>
<updated>2016-07-15T04:22:45Z</updated>
<author>
<name>Sergei Shtylyov</name>
<email>sergei.shtylyov@cogentembedded.com</email>
</author>
<published>2016-07-11T21:52:43Z</published>
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<id>urn:sha1:e0c3f92a08f3e0a95024d0d032564fdc1ee96f54</id>
<content type='text'>
Simon Horman told me that R8A7792 has ADSP clock based on an incorrect
table in the most recent R-Car gen2 manual. But when I received that manual
I discovered that this is false: R8A7792 is the only Gen 2 SoC that doesn't
have ADSP at all.  Accordingly remove the ADSP clock from DT for the
r8a7792.

Signed-off-by: Sergei Shtylyov &lt;sergei.shtylyov@cogentembedded.com&gt;
Reviewed-by: Geert Uytterhoeven &lt;geert+renesas@glider.be&gt;
Signed-off-by: Simon Horman &lt;horms+renesas@verge.net.au&gt;
</content>
</entry>
<entry>
<title>ARM: dts: r8a7792: add JPU clocks</title>
<updated>2016-06-24T02:04:35Z</updated>
<author>
<name>Sergei Shtylyov</name>
<email>sergei.shtylyov@cogentembedded.com</email>
</author>
<published>2016-06-16T22:02:48Z</published>
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<id>urn:sha1:eebc8e2c5b7a3db19075a02730db8b73be933485</id>
<content type='text'>
Add JPU clock and its parent, M2 clock to the R8A7792 device tree.

Signed-off-by: Sergei Shtylyov &lt;sergei.shtylyov@cogentembedded.com&gt;
Reviewed-by: Geert Uytterhoeven &lt;geert+renesas@glider.be&gt;
Signed-off-by: Simon Horman &lt;horms+renesas@verge.net.au&gt;
</content>
</entry>
<entry>
<title>ARM: dts: r8a7792: add clock index macros</title>
<updated>2016-06-16T00:25:13Z</updated>
<author>
<name>Sergei Shtylyov</name>
<email>sergei.shtylyov@cogentembedded.com</email>
</author>
<published>2016-06-12T20:53:04Z</published>
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<id>urn:sha1:de0fae60b35d405d3aa2e9acf5914770cd328338</id>
<content type='text'>
Add macros usable by the device tree sources to reference the R8A7792
clocks  by index.

Signed-off-by: Sergei Shtylyov &lt;sergei.shtylyov@cogentembedded.com&gt;
Reviewed-by: Geert Uytterhoeven &lt;geert+renesas@glider.be&gt;
Signed-off-by: Simon Horman &lt;horms+renesas@verge.net.au&gt;
</content>
</entry>
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