<feed xmlns='http://www.w3.org/2005/Atom'>
<title>kernel/include/dt-bindings/clock/mt8173-clk.h, branch linux-4.15.y</title>
<subtitle>Hosts the 0x221E linux distro kernel.</subtitle>
<id>https://universe.0xinfinity.dev/distro/kernel/atom?h=linux-4.15.y</id>
<link rel='self' href='https://universe.0xinfinity.dev/distro/kernel/atom?h=linux-4.15.y'/>
<link rel='alternate' type='text/html' href='https://universe.0xinfinity.dev/distro/kernel/'/>
<updated>2017-06-20T02:02:44Z</updated>
<entry>
<title>clk: mediatek: export cpu multiplexer clock for MT8173 SoCs</title>
<updated>2017-06-20T02:02:44Z</updated>
<author>
<name>Sean Wang</name>
<email>sean.wang@mediatek.com</email>
</author>
<published>2017-05-05T15:26:11Z</published>
<link rel='alternate' type='text/html' href='https://universe.0xinfinity.dev/distro/kernel/commit/?id=567bf2ed86d13aecfb7d3c1ab75166193ce37213'/>
<id>urn:sha1:567bf2ed86d13aecfb7d3c1ab75166193ce37213</id>
<content type='text'>
The patch enables CPU multiplexer clock on MT8173 SoC which fixes up
cpufreq driver fails at acquiring intermediate clock source when driver
probe is called.

Signed-off-by: Pi-Cheng Chen &lt;pi-cheng.chen@linaro.org&gt;
Signed-off-by: Sean Wang &lt;sean.wang@mediatek.com&gt;
Signed-off-by: Stephen Boyd &lt;sboyd@codeaurora.org&gt;
</content>
</entry>
<entry>
<title>clk: mediatek: Add hdmi_ref HDMI PHY PLL reference clock output</title>
<updated>2016-05-06T15:47:40Z</updated>
<author>
<name>Philipp Zabel</name>
<email>p.zabel@pengutronix.de</email>
</author>
<published>2015-11-30T21:07:53Z</published>
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<id>urn:sha1:4585945bf1d348d006f7270beea3dae09fee3413</id>
<content type='text'>
The configurable hdmi_ref output of the PLL block is derived from
the tvdpll_594m clock signal via a configurable PLL post-divider.
It is used as the PLL reference input to the HDMI PHY module.

Signed-off-by: Philipp Zabel &lt;p.zabel@pengutronix.de&gt;
Acked-by: James Liao &lt;jamesjj.liao@mediatek.com&gt;
Acked-by: Stephen Boyd &lt;sboyd@codeaurora.org&gt;
</content>
</entry>
<entry>
<title>clk: mediatek: Add USB clock support in MT8173 APMIXEDSYS</title>
<updated>2015-10-01T04:06:00Z</updated>
<author>
<name>James Liao</name>
<email>jamesjj.liao@mediatek.com</email>
</author>
<published>2015-05-20T07:59:21Z</published>
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<id>urn:sha1:cdb2bab78aff97101da767b9643fbd692af4623b</id>
<content type='text'>
Add REF2USB_TX clock support into MT8173 APMIXEDSYS. This clock
is needed by USB 3.0.

Signed-off-by: James Liao &lt;jamesjj.liao@mediatek.com&gt;
Reviewed-by: Daniel Kurtz &lt;djkurtz@chromium.org&gt;
</content>
</entry>
<entry>
<title>clk: mediatek: Add subsystem clocks of MT8173</title>
<updated>2015-10-01T04:04:50Z</updated>
<author>
<name>James Liao</name>
<email>jamesjj.liao@mediatek.com</email>
</author>
<published>2015-05-20T06:45:54Z</published>
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<id>urn:sha1:29859d9315834c7a36a436a6a383f2f810b91047</id>
<content type='text'>
Most multimedia subsystem clocks will be accessed by multiple
drivers, so it's a better way to manage these clocks in CCF.
This patch adds clock support for MM, IMG, VDEC, VENC and VENC_LT
subsystems.

Signed-off-by: James Liao &lt;jamesjj.liao@mediatek.com&gt;
Reviewed-by: Daniel Kurtz &lt;djkurtz@chromium.org&gt;
</content>
</entry>
<entry>
<title>clk: mediatek: Removed unused dpi_ck clock from MT8173</title>
<updated>2015-10-01T04:04:48Z</updated>
<author>
<name>James Liao</name>
<email>jamesjj.liao@mediatek.com</email>
</author>
<published>2015-07-28T06:30:03Z</published>
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<id>urn:sha1:829f4912d1577f6ee68274fcb678f9da0b760244</id>
<content type='text'>
The dpi_ck clock can be removed because it not actually used
in topckgen and subsystems.

Signed-off-by: James Liao &lt;jamesjj.liao@mediatek.com&gt;
Reviewed-by: Daniel Kurtz &lt;djkurtz@chromium.org&gt;
</content>
</entry>
<entry>
<title>clk: mediatek: add 13mhz clock for MT8173</title>
<updated>2015-10-01T04:04:34Z</updated>
<author>
<name>Joe.C</name>
<email>yingjoe.chen@mediatek.com</email>
</author>
<published>2015-07-13T09:32:48Z</published>
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<id>urn:sha1:2d61fe0fc7f0a8c214587ba063fc8770486c0af1</id>
<content type='text'>
Add 13mhz clock used by GPT timer in infracfg.

Signed-off-by: Yingjoe Chen &lt;yingjoe.chen@mediatek.com&gt;
Acked-by: Stephen Boyd &lt;sboyd@codeaurora.org&gt;
Signed-off-by: James Liao &lt;jamesjj.liao@mediatek.com&gt;
</content>
</entry>
<entry>
<title>clk: mediatek: Add basic clocks for Mediatek MT8173.</title>
<updated>2015-05-06T05:50:38Z</updated>
<author>
<name>James Liao</name>
<email>jamesjj.liao@mediatek.com</email>
</author>
<published>2015-04-23T08:35:42Z</published>
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<id>urn:sha1:c1e81a3bef36cb046c079480948fa3e0eca590d6</id>
<content type='text'>
This patch adds basic clocks for MT8173, including TOPCKGEN, PLLs,
INFRA and PERI clocks.

Signed-off-by: James Liao &lt;jamesjj.liao@mediatek.com&gt;
Signed-off-by: Henry Chen &lt;henryc.chen@mediatek.com&gt;
Signed-off-by: Sascha Hauer &lt;s.hauer@pengutronix.de&gt;
Signed-off-by: Stephen Boyd &lt;sboyd@codeaurora.org&gt;
</content>
</entry>
</feed>
