<feed xmlns='http://www.w3.org/2005/Atom'>
<title>kernel/include/dt-bindings/clock/mt2701-clk.h, branch linux-4.16.y</title>
<subtitle>Hosts the 0x221E linux distro kernel.</subtitle>
<id>https://universe.0xinfinity.dev/distro/kernel/atom?h=linux-4.16.y</id>
<link rel='self' href='https://universe.0xinfinity.dev/distro/kernel/atom?h=linux-4.16.y'/>
<link rel='alternate' type='text/html' href='https://universe.0xinfinity.dev/distro/kernel/'/>
<updated>2018-04-24T07:43:05Z</updated>
<entry>
<title>dt-bindings: clock: mediatek: add binding for fixed-factor clock axisel_d4</title>
<updated>2018-04-24T07:43:05Z</updated>
<author>
<name>Sean Wang</name>
<email>sean.wang@mediatek.com</email>
</author>
<published>2018-03-01T03:27:50Z</published>
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<id>urn:sha1:525398643e51065ae209f17884bd0d695b6cb59b</id>
<content type='text'>
commit 55a5fcafe3a94e8a0777bb993d09107d362258d2 upstream.

Just add binding for a fixed-factor clock axisel_d4, which would be
referenced by PWM devices on MT7623 or MT2701 SoC.

Cc: stable@vger.kernel.org
Fixes: 1de9b21633d6 ("clk: mediatek: Add dt-bindings for MT2701 clocks")
Signed-off-by: Sean Wang &lt;sean.wang@mediatek.com&gt;
Reviewed-by: Rob Herring &lt;robh@kernel.org&gt;
Cc: Mark Rutland &lt;mark.rutland@arm.com&gt;
Cc: devicetree@vger.kernel.org
Signed-off-by: Stephen Boyd &lt;sboyd@kernel.org&gt;
Signed-off-by: Greg Kroah-Hartman &lt;gregkh@linuxfoundation.org&gt;

</content>
</entry>
<entry>
<title>clk: mediatek: export cpu multiplexer clock for MT2701/MT7623 SoCs</title>
<updated>2017-06-20T02:02:44Z</updated>
<author>
<name>Sean Wang</name>
<email>sean.wang@mediatek.com</email>
</author>
<published>2017-05-05T15:26:10Z</published>
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<id>urn:sha1:43ed50ee5a181fcfbdeb7566f5e8122bad182889</id>
<content type='text'>
The patch enables CPU multiplexer clock on MT2701/MT7623 SoC which fixes
up cpufreq driver fails at acquiring intermediate clock source when driver
probe is called.

Signed-off-by: Pi-Cheng Chen &lt;pi-cheng.chen@linaro.org&gt;
Signed-off-by: Sean Wang &lt;sean.wang@mediatek.com&gt;
Signed-off-by: Stephen Boyd &lt;sboyd@codeaurora.org&gt;
</content>
</entry>
<entry>
<title>clk: mediatek: Add dt-bindings for MT2701 clocks</title>
<updated>2016-08-19T19:18:41Z</updated>
<author>
<name>Shunli Wang</name>
<email>shunli.wang@mediatek.com</email>
</author>
<published>2016-08-19T05:34:51Z</published>
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<id>urn:sha1:1de9b21633d669668b089bc88a67c4cd74a89a1c</id>
<content type='text'>
Add MT2701 clock dt-bindings, include topckgen, apmixedsys,
infracfg, pericfg and subsystem clocks.

Signed-off-by: Shunli Wang &lt;shunli.wang@mediatek.com&gt;
Signed-off-by: James Liao &lt;jamesjj.liao@mediatek.com&gt;
Signed-off-by: Erin Lo &lt;erin.lo@mediatek.com&gt;
Tested-by: John Crispin &lt;blogic@openwrt.org&gt;
Reviewed-by: Matthias Brugger &lt;matthias.bgg@gmail.com&gt;
Signed-off-by: Stephen Boyd &lt;sboyd@codeaurora.org&gt;
</content>
</entry>
</feed>
