<feed xmlns='http://www.w3.org/2005/Atom'>
<title>kernel/include/dt-bindings/clock/imx8mq-clock.h, branch linux-6.2.y</title>
<subtitle>Hosts the 0x221E linux distro kernel.</subtitle>
<id>https://universe.0xinfinity.dev/distro/kernel/atom?h=linux-6.2.y</id>
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<updated>2021-06-14T14:05:45Z</updated>
<entry>
<title>clk: imx8mq: remove SYS PLL 1/2 clock gates</title>
<updated>2021-06-14T14:05:45Z</updated>
<author>
<name>Lucas Stach</name>
<email>l.stach@pengutronix.de</email>
</author>
<published>2021-05-28T18:01:35Z</published>
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<id>urn:sha1:c586f53ae159c6c1390f093a1ec94baef2df9f3a</id>
<content type='text'>
Remove the PLL clock gates as the allowing to gate the sys1_pll_266m breaks
the uSDHC module which is sporadically unable to enumerate devices after
this change. Also it makes AMP clock management harder with no obvious
benefit to Linux, so just revert the change.

Link: https://lore.kernel.org/r/20210528180135.1640876-1-l.stach@pengutronix.de
Fixes: b04383b6a558 ("clk: imx8mq: Define gates for pll1/2 fixed dividers")
Signed-off-by: Lucas Stach &lt;l.stach@pengutronix.de&gt;
Reviewed-by: Abel Vesa &lt;abel.vesa@nxp.com&gt;
Signed-off-by: Abel Vesa &lt;abel.vesa@nxp.com&gt;
</content>
</entry>
<entry>
<title>clk: imx8mq: add PLL monitor output</title>
<updated>2021-01-30T13:35:15Z</updated>
<author>
<name>Lucas Stach</name>
<email>l.stach@pengutronix.de</email>
</author>
<published>2021-01-25T17:41:33Z</published>
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<id>urn:sha1:75a352bc6611e79227328e39d42086b0eebf24f3</id>
<content type='text'>
The PLL monitor is mentioned as a debug feature in the reference manual,
but there are some boards that use this clock output as a reference clock
for board level components. Add support for those clocks in the clock
driver, so this clock output can be used properly.

Note that the VIDEO1, GPU and VPU mux inputs are rotated compared to the
description in the reference manual. The order in this patch has been
empirically validated.

Signed-off-by: Lucas Stach &lt;l.stach@pengutronix.de&gt;
Reviewed-by: Abel Vesa &lt;abel.vesa@nxp.com&gt;
Signed-off-by: Shawn Guo &lt;shawnguo@kernel.org&gt;
</content>
</entry>
<entry>
<title>clk: imx: imx8mq: fix a53 cpu clock</title>
<updated>2020-02-24T07:39:56Z</updated>
<author>
<name>Peng Fan</name>
<email>peng.fan@nxp.com</email>
</author>
<published>2020-02-19T10:17:06Z</published>
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<id>urn:sha1:d6fb02f054127c23b048f4753176c57f3e440e79</id>
<content type='text'>
The A53 CCM clk root only accepts input up to 1GHz, CCM A53 root
signoff timing is 1Ghz, however the A53 core which sources from CCM
root could run above 1GHz which violates the CCM.

There is a CORE_SEL slice before A53 core, we need to configure the
CORE_SEL slice source from ARM PLL, not A53 CCM clk root.

The A53 CCM clk root should only be used when need to change ARM PLL
frequency.

Add arm_a53_core clk that could source from arm_a53_div and arm_pll_out.
Configure a53 ccm root sources from 800MHz sys pll
Configure a53 core sources from arm_pll_out
Mark arm_a53_core as critical clock

Fixes: db27e40b27f1 ("clk: imx8mq: Add the missing ARM clock")
Reviewed-by: Jacky Bai &lt;ping.bai@nxp.com&gt;
Signed-off-by: Peng Fan &lt;peng.fan@nxp.com&gt;
Signed-off-by: Shawn Guo &lt;shawnguo@kernel.org&gt;
</content>
</entry>
<entry>
<title>clk: imx: imx8mq: use imx8m_clk_hw_composite_core</title>
<updated>2020-02-14T02:49:35Z</updated>
<author>
<name>Peng Fan</name>
<email>peng.fan@nxp.com</email>
</author>
<published>2020-01-28T05:28:41Z</published>
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<id>urn:sha1:7a8d3b90bdfe44d2e90523444ff82f0060d9560e</id>
<content type='text'>
Use imx8m_clk_hw_composite_core to simplify code.

Add new definitions, and X_SRC/CG/DIV will be alias to the new
definitions for backwards compatibility

Reviewed-by: Abel Vesa &lt;abel.vesa@nxp.com&gt;
Signed-off-by: Peng Fan &lt;peng.fan@nxp.com&gt;
Reviewed-by: Leonard Crestez &lt;leonard.crestez@nxp.com&gt;
Signed-off-by: Shawn Guo &lt;shawnguo@kernel.org&gt;
</content>
</entry>
<entry>
<title>clk: imx8mq: Define gates for pll1/2 fixed dividers</title>
<updated>2019-10-25T09:03:00Z</updated>
<author>
<name>Leonard Crestez</name>
<email>leonard.crestez@nxp.com</email>
</author>
<published>2019-10-16T11:57:37Z</published>
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<id>urn:sha1:b04383b6a5588906ffd059a6a9f5344a9c6df58a</id>
<content type='text'>
On imx8mq there are 9 fixed-factor dividers for SYS_PLL1 and SYS_PLL2
each with their own gate but these gates are not currently defined in
the clock tree.

Add them between sys1/2_pll_out and the fixed dividers.

Signed-off-by: Leonard Crestez &lt;leonard.crestez@nxp.com&gt;
Reviewed-by: Abel Vesa &lt;abel.vesa@nxp.com&gt;
Signed-off-by: Shawn Guo &lt;shawnguo@kernel.org&gt;
</content>
</entry>
<entry>
<title>clk: imx8mq: Add VIDEO2_PLL clock</title>
<updated>2019-10-14T11:27:23Z</updated>
<author>
<name>Laurentiu Palcu</name>
<email>laurentiu.palcu@nxp.com</email>
</author>
<published>2019-10-02T14:04:53Z</published>
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<id>urn:sha1:f0b1d7f2e7c2348ae4c856dffb6172c80a023483</id>
<content type='text'>
This clock is needed by DCSS when high resolutions are used.

Signed-off-by: Laurentiu Palcu &lt;laurentiu.palcu@nxp.com&gt;
CC: Abel Vesa &lt;abel.vesa@nxp.com&gt;
Signed-off-by: Shawn Guo &lt;shawnguo@kernel.org&gt;
</content>
</entry>
<entry>
<title>dt-bindings: clock: imx8m: Add GIC clock</title>
<updated>2019-05-23T13:14:40Z</updated>
<author>
<name>Leonard Crestez</name>
<email>leonard.crestez@nxp.com</email>
</author>
<published>2019-05-22T09:48:29Z</published>
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<id>urn:sha1:87def8d0d5bfc32bf8a221b63addb8a051cbf017</id>
<content type='text'>
This should be defined in the clock tree so that parents are not
shutdown by accident

Signed-off-by: Leonard Crestez &lt;leonard.crestez@nxp.com&gt;
Reviewed-by: Abel Vesa &lt;abel.vesa@nxp.com&gt;
Signed-off-by: Shawn Guo &lt;shawnguo@kernel.org&gt;
</content>
</entry>
<entry>
<title>dt-bindings: clock: imx8mq: Add SNVS clock</title>
<updated>2019-05-22T09:00:52Z</updated>
<author>
<name>Anson Huang</name>
<email>anson.huang@nxp.com</email>
</author>
<published>2019-05-15T01:09:24Z</published>
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<id>urn:sha1:4ef69160b3ed62379ef853c512d3785bf2ea57e6</id>
<content type='text'>
Add macro for the SNVS clock of the i.MX8MQ.

Signed-off-by: Anson Huang &lt;Anson.Huang@nxp.com&gt;
Reviewed-by: Leonard Crestez &lt;leonard.crestez@nxp.com&gt;
Signed-off-by: Shawn Guo &lt;shawnguo@kernel.org&gt;
</content>
</entry>
<entry>
<title>dt-bindings: clock: imx8mq: Fix numbering overlaps and gaps</title>
<updated>2019-03-12T20:40:10Z</updated>
<author>
<name>Abel Vesa</name>
<email>abel.vesa@nxp.com</email>
</author>
<published>2019-03-05T09:49:16Z</published>
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<id>urn:sha1:010d5166bbe95523e8584f3caca9f1bbeac9ea6e</id>
<content type='text'>
IMX8MQ_CLK_USB_PHY_REF changes from 163 to 153, this way removing the gap.
All the following clock ids are now decreased by 10 to keep the numbering
right. Doing this, the IMX8MQ_CLK_CSI2_CORE is not overlapped with
IMX8MQ_CLK_GPT1 anymore. IMX8MQ_CLK_GPT1_ROOT changes from 193 to 183 and
all the following ids are updated accordingly.

Reported-by: Patrick Wildt &lt;patrick@blueri.se&gt;
Fixes: 1cf3817b ("dt-bindings: Add binding for i.MX8MQ CCM")
Signed-off-by: Abel Vesa &lt;abel.vesa@nxp.com&gt;
Signed-off-by: Stephen Boyd &lt;sboyd@kernel.org&gt;
</content>
</entry>
<entry>
<title>clk: imx8mq: add GPIO clocks to clock tree</title>
<updated>2019-02-28T18:28:28Z</updated>
<author>
<name>Anson Huang</name>
<email>anson.huang@nxp.com</email>
</author>
<published>2019-02-27T01:28:26Z</published>
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<id>urn:sha1:0c91c11c7d62de9fea6f5520edb143a7199f3307</id>
<content type='text'>
i.MX8MQ has clock gate for each GPIO bank, add them
into clock tree for GPIO driver to manage.

Signed-off-by: Anson Huang &lt;Anson.Huang@nxp.com&gt;
Reviewed-by: Fabio Estevam &lt;festevam@gmail.com&gt;
Signed-off-by: Stephen Boyd &lt;sboyd@kernel.org&gt;
</content>
</entry>
</feed>
