kernel/include/dt-bindings/clock/imx8mp-clock.h, branch linux-6.2.y

dt-bindings: clock: imx8mp: Add ids for the audio shared gate

2022-11-21T22:04:49Z

All these IDs are for one single HW gate (CCGR101) that is shared between these root clocks. Signed-off-by: Abel Vesa Signed-off-by: Shengjiu Wang Reviewed-by: Peng Fan Acked-by: Krzysztof Kozlowski Reviewed-by: Abel Vesa Signed-off-by: Abel Vesa Link: https://lore.kernel.org/r/1667811007-19222-2-git-send-email-shengjiu.wang@nxp.com

dt-bindings: clocks: imx8mp: Add ID for usb suspend clock

2022-11-21T15:56:06Z

usb suspend clock has a gate shared with usb_root_clk. Fixes: 9c140d9926761 ("clk: imx: Add support for i.MX8MP clock driver") Cc: stable@vger.kernel.org # v5.19+ Acked-by: Krzysztof Kozlowski Tested-by: Alexander Stein Signed-off-by: Li Jun Signed-off-by: Abel Vesa Link: https://lore.kernel.org/r/1664549663-20364-1-git-send-email-jun.li@nxp.com

clk: imx8mp: add clkout1/2 support

2022-05-02T09:38:10Z

clkout1 and clkout2 allow to supply clocks from the SoC to the board, which is used by some board designs to provide reference clocks. Signed-off-by: Lucas Stach Reviewed-by: Abel Vesa Link: https://lore.kernel.org/r/20220427162131.3127303-1-l.stach@pengutronix.de Signed-off-by: Abel Vesa

clk: imx8mp: Add DISP2 pixel clock

2022-04-18T09:51:04Z

Add pixel clock for second LCDIFv3 interface. Both LCDIFv3 interfaces use the same set of parent clock, so deduplicate imx8mp_media_disp1_pix_sels into common imx8mp_media_disp_pix_sels and use it for both. Signed-off-by: Marek Vasut Cc: Abel Vesa Cc: Fabio Estevam Cc: NXP Linux Team Cc: Peng Fan Cc: Shawn Guo Reviewed-by: Abel Vesa Link: https://lore.kernel.org/r/20220313123949.207284-1-marex@denx.de Signed-off-by: Abel Vesa

clk: imx8mp: Remove IPG_AUDIO_ROOT from imx8mp-clock.h

2021-11-22T15:06:48Z

Since the commit b24e288d5063 ("clk: imx: Remove the audio ipg clock from imx8mp") removes the non-existing IPG_AUDIO_ROOT from the clk-imx8mp.c, and this definition is not used by anywhere, let us removed it in the imx8mp-clock.h as well. Signed-off-by: Hui Wang Reviewed-by: Abel Vesa Link: https://lore.kernel.org/r/20211109125657.63485-1-hui.wang@canonical.com Signed-off-by: Abel Vesa

clk: imx8mp: Remove the none exist pcie clocks

2021-04-04T19:39:04Z

In the i.MX8MP PCIe design, the PCIe PHY REF clock comes from external OSC or internal system PLL. It is configured in the IOMUX_GPR14 register directly, and can't be contolled by CCM at all. Remove the PCIE PHY clock from clock driver to clean up codes. There is only one PCIe in i.MX8MP, remove the none exist second PCIe related clocks. Remove the none exsits clocks IDs together. Signed-off-by: Richard Zhu Reviewed-by: Jason Liu Signed-off-by: Abel Vesa

clk: imx: Correct the root clk of media ldb on imx8mp

2020-08-31T02:26:57Z

The root clock slice at 0xbf00 is media_ldb clock, not csi_phy2_ref, so correct it. Signed-off-by: Jacky Bai Signed-off-by: Shawn Guo

clk: imx8mp: use imx8m_clk_hw_composite_core to simplify code

2020-05-20T01:26:48Z

Use imx8m_clk_hw_composite_core to simpliy clks that belong to core clk slice. Reviewed-by: Leonard Crestez Signed-off-by: Peng Fan Reviewed-by: Dong Aisheng Signed-off-by: Shawn Guo

clk: imx8mp: Define gates for pll1/2 fixed dividers

2020-05-20T01:26:45Z

Inspried from commit e8688fe8df7d ("clk: imx8mn: Define gates for pll1/2 fixed dividers") On imx8mp there are 9 fixed-factor dividers for SYS_PLL1 and SYS_PLL2 each with their own gate. Only one of these gates (the one "dividing" by one) is currently defined and it's incorrectly set as the parent of all the fixed-factor dividers. Add the other 8 gates to the clock tree between sys_pll1/2_bypass and the fixed dividers. Reviewed-by: Dong Aisheng Reviewed-by: Leonard Crestez Signed-off-by: Peng Fan Signed-off-by: Shawn Guo

dt-bindings: clocks: imx8mp: Add ids for audiomix clocks

2020-04-29T02:01:57Z

Add all the clock ids for the audiomix clocks. Signed-off-by: Abel Vesa Acked-by: Rob Herring Reviewed-by: Stephen Boyd Signed-off-by: Shawn Guo