kernel/include/dt-bindings/clock/imx8mm-clock.h, branch linux-6.2.y

dt-bindings: clk: imx8mm: don't use multiple blank lines

2022-09-17T08:25:05Z

Avoid the following checkpatch warning: include/dt-bindings/clock/imx8mm-clock.h:284: check: Please don't use multiple blank lines Signed-off-by: Marcel Ziswiler Reviewed-by: Fabio Estevam Signed-off-by: Shawn Guo

clk: imx8mm: add clkout1/2 support

2021-01-30T13:35:30Z

clkout1 and clkout2 allow to supply clocks from the SoC to the board, which is used by some board designs to provide reference clocks. Signed-off-by: Lucas Stach Reviewed-by: Abel Vesa Signed-off-by: Shawn Guo

clk: imx: imx8mm: fix a53 cpu clock

2020-02-24T07:39:56Z

The A53 CCM clk root only accepts input up to 1GHz, CCM A53 root signoff timing is 1Ghz, however the A53 core which sources from CCM root could run above 1GHz which voilates the CCM. There is a CORE_SEL slice before A53 core, we need configure the CORE_SEL slice source from ARM PLL, not A53 CCM clk root. The A53 CCM clk root should only be used when need to change ARM PLL frequency. Add arm_a53_core clk that could source from arm_a53_div and arm_pll_out. Configure a53 ccm root sources from 800MHz sys pll Configure a53 core sources from arm_pll_out Mark arm_a53_core as critical clock Fixes: ba5625c3e272 ("clk: imx: Add clock driver support for imx8mm") Reviewed-by: Jacky Bai Signed-off-by: Peng Fan Signed-off-by: Shawn Guo

clk: imx8mm: Add CLKO2 support

2020-02-17T05:49:38Z

Add CLKO2 support, which is useful for debugging purposes. Signed-off-by: Fabio Estevam Reviewed-by: Abel Vesa Signed-off-by: Shawn Guo

clk: imx: imx8mm: use imx8m_clk_hw_composite_core

2020-02-14T02:49:38Z

Use imx8m_clk_hw_composite_core to simplify code. Add new definitions, and X_SRC/CG/DIV will be alias to the new definitions for backwards compatibility Reviewed-by: Abel Vesa Signed-off-by: Peng Fan Reviewed-by: Leonard Crestez Signed-off-by: Shawn Guo

clk: imx8mm: Define gates for pll1/2 fixed dividers

2019-10-25T09:03:16Z

On imx8mm there are 9 fixed-factor dividers for SYS_PLL1 and SYS_PLL2 each with their own gate. Only one of these gates (the one "dividing" by one) is currently defined and it's incorrectly set as the parent of all the fixed-factor dividers. Add the other 8 gates to the clock tree between sys_pll1/2_bypass and the fixed dividers. Signed-off-by: Leonard Crestez Reviewed-by: Abel Vesa Signed-off-by: Shawn Guo

dt-bindings: clock: imx8m: Add GIC clock

2019-05-23T13:14:40Z

This should be defined in the clock tree so that parents are not shutdown by accident Signed-off-by: Leonard Crestez Reviewed-by: Abel Vesa Signed-off-by: Shawn Guo

dt-bindings: clock: imx8mm: Add SNVS clock

2019-05-23T07:29:39Z

Add macro for the SNVS clock of the i.MX8MM. Signed-off-by: Anson Huang Reviewed-by: Leonard Crestez Signed-off-by: Shawn Guo

dt-bindings: clock: imx8mm: Add GPIO clocks

2019-05-20T03:21:35Z

Add macro for the GPIO clocks of the i.MX8MM. Signed-off-by: Anson Huang Reviewed-by: Dong Aisheng Signed-off-by: Shawn Guo

dt-bindings: imx: Add clock binding doc for imx8mm

2019-02-21T20:41:16Z

Add the clock binding doc for i.MX8MM. Signed-off-by: Bai Ping Reviewed-by: Rob Herring Signed-off-by: Stephen Boyd