kernel/include/dt-bindings/clock/imx7d-clock.h, branch linux-5.11.y

clk: imx7d: Add PXP clock

2020-03-16T00:56:59Z

The PXP has a single CCGR clock gate, gating both the IPG_CLK_ROOT and the MAIN_AXI_CLK_ROOT. Add a single clock to cover both. Signed-off-by: Laurent Pinchart Signed-off-by: Shawn Guo

treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 500

2019-06-19T15:09:55Z

Based on 2 normalized pattern(s): this program is free software you can redistribute it and or modify it under the terms of the gnu general public license version 2 as published by the free software foundation this program is free software you can redistribute it and or modify it under the terms of the gnu general public license version 2 as published by the free software foundation # extracted by the scancode license scanner the SPDX license identifier GPL-2.0-only has been chosen to replace the boilerplate/reference in 4122 file(s). Signed-off-by: Thomas Gleixner Reviewed-by: Enrico Weigelt Reviewed-by: Kate Stewart Reviewed-by: Allison Randal Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190604081206.933168790@linutronix.de Signed-off-by: Greg Kroah-Hartman

clk: imx7d: correct enet clock CCGR registers

2018-06-01T19:15:21Z

Correct enet clock gates as below: CCGR6: IMX7D_ENET_AXI_ROOT_CLK (enet1 and enet2 bus clocks) CCGR112: IMX7D_ENET1_TIME_ROOT_CLK, IMX7D_ENET1_IPG_ROOT_CLK CCGR113: IMX7D_ENET2_TIME_ROOT_CLK, IMX7D_ENET2_IPG_ROOT_CLK Just rename unused IMX7D_ENETx_REF_ROOT_CLK for IMX7D_ENETx_IPG_ROOT_CLK instead of adding new clocks. Based on Andy Duan's patch from the NXP kernel tree. Signed-off-by: Anson Huang Acked-by: Rob Herring Reviewed-by: Stefan Agner Signed-off-by: Stephen Boyd

clk: imx: imx7d: add the Keypad Port module clock

2018-02-28T06:43:00Z

According to the i.MX7D Reference Manual, the Keypad Port module (KPP) requires this clock gate to be enabled. Signed-off-by: Stefan Agner Signed-off-by: Shawn Guo

clk: imx7d: add CAAM clock

2018-02-28T01:17:41Z

Add CAAM clock so that we could use the Cryptographic Acceleration and Assurance Module (CAAM) hardware block. Cc: Michael Turquette Cc: Stephen Boyd Cc: linux-clk@vger.kernel.org Cc: "Horia Geantă" Cc: Aymen Sghaier Cc: Fabio Estevam Cc: Peng Fan Cc: "David S. Miller" Cc: Lukas Auer Reviewed-by: Fabio Estevam Signed-off-by: Rui Miguel Silva Signed-off-by: Shawn Guo

clk: imx: imx7d: add the snvs clock

2018-02-22T09:46:58Z

According to the i.MX7D Reference Manual, SNVS block has a clock gate, accessing SNVS block would need this clock gate to be enabled, add it into clock tree so that SNVS module driver can operate this clock gate. Signed-off-by: Anson Huang Acked-by: Dong Aisheng Reviewed-by: Fabio Estevam Signed-off-by: Shawn Guo

clk: imx: imx7d: Remove ARM_M0 clock

2017-11-02T07:26:18Z

IMX7d does not have an M0 Core and this particular clock doesn't seem connected to anything else. Remove this entry from the CCM driver. Signed-off-by: Adriana Reus Signed-off-by: Stephen Boyd

clk: imx7d: create clocks behind rawnand clock gate

2017-06-20T02:02:41Z

The rawnand clock gate gates two clocks, NAND_USDHC_BUS_CLK_ROOT and NAND_CLK_ROOT. However, the gate has been in the chain of the latter only. This does not allow to use the NAND_USDHC_BUS_CLK_ROOT only, e.g. as required by APBH-Bridge-DMA. Add new clocks which represent the clock after the gate, and use a shared clock gate to correctly model the hardware. Signed-off-by: Stefan Agner Tested-by: Fabio Estevam Acked-by: Han Xu Signed-off-by: Stephen Boyd

clk: imx7d: Add the OCOTP clock

2017-01-21T00:27:19Z

Add the OCOTP so that this hardware block can be used. Signed-off-by: Fabio Estevam Signed-off-by: Stephen Boyd

clk: imx: add ckil clock for i.MX7

2016-04-06T09:04:26Z

Add the necessary clock to use the ckil on i.MX7. Inspired from the following patch: https://github.com/boundarydevices/linux-imx6/commit/b80e8271 Signed-off-by: Troy Kisky Signed-off-by: Gary Bisson Signed-off-by: Shawn Guo