kernel/include/dt-bindings/clock/imx6sl-clock.h, branch linux-5.11.y

treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 500

2019-06-19T15:09:55Z

Based on 2 normalized pattern(s): this program is free software you can redistribute it and or modify it under the terms of the gnu general public license version 2 as published by the free software foundation this program is free software you can redistribute it and or modify it under the terms of the gnu general public license version 2 as published by the free software foundation # extracted by the scancode license scanner the SPDX license identifier GPL-2.0-only has been chosen to replace the boilerplate/reference in 4122 file(s). Signed-off-by: Thomas Gleixner Reviewed-by: Enrico Weigelt Reviewed-by: Kate Stewart Reviewed-by: Allison Randal Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190604081206.933168790@linutronix.de Signed-off-by: Greg Kroah-Hartman

clk: imx6sl: add mmdc ipg clocks

2018-10-17T18:15:51Z

i.MX6SL has MMDC0 and MMDC1 ipg clock in CCM CCGR, add them into clock tree for clock management. Signed-off-by: Anson Huang Reviewed-by: Rob Herring Signed-off-by: Stephen Boyd

clk: imx6: Add SPDIF_GCLK clock in clock tree

2015-10-12T13:55:59Z

Correct SPDIF clock setting issue in clock tree, the SPDIF_GCLK is also one clock of SPDIF, which is missed before. We found an issue that imx can't enter low power mode with spdif if IMX6x_CLK_SPDIF is used as the core clock of spdif. Because spdif driver will register IMX6x_CLK_SPDIF clock to regmap, regmap will do clk_prepare in init function, then IMX6x_CLK_SPDIF clock is prepared in probe, so its parent clock (PLL clock) is prepared, the prepare operation of PLL clock is to enable the clock. But I.MX needs all PLL clock is disabled, then it can enter low power mode. So we can't use IMX6x_CLK_SPDIF as the core clock of spdif, the correct spdif core clock is SPDIF_GCLK, which share same gate bit with IMX6x_CLK_SPDIF clock. SPDIF_GCLK's parent clock is ipg clock. Signed-off-by: Shengjiu Wang Signed-off-by: Shawn Guo

ARM: clk-imx6sl: refine clock tree for SSI

2014-09-16T02:09:39Z

Each SSI has "ssi", "ssi_ipg" clocks, and they share same gate bits. Signed-off-by: Shengjiu Wang Signed-off-by: Shawn Guo

ARM: imx6sl: add BYPASS support for PLL clocks

2014-09-16T02:06:48Z

This is the same change for imx6sl clock driver as "ARM: imx6q: add BYPASS support for PLL clocks" for imx6q. The difference is that only anaclk1 is available on imx6sl. Signed-off-by: Shawn Guo

ARM: imx6sl: add missing enet clock for imx6sl

2014-06-17T13:11:18Z

There's a enet clock gate missing in clock tree, thus add it. Signed-off-by: Fugang Duan Signed-off-by: Shawn Guo

ARM: imx6sl: Add missing spba clock to clock tree

2013-12-31T01:36:37Z

We are missing spba clock in imx6sl's clock tree, thus add it. Signed-off-by: Nicolin Chen Signed-off-by: Shawn Guo

ARM: imx6sl: Add missing pll4_audio_div to the clock tree

2013-12-31T01:36:36Z

There's a dividor for pll4_audio clock missing in clock tree, thus add it. Signed-off-by: Nicolin Chen Signed-off-by: Shawn Guo

ARM: imx: rename IMX6SL_CLK_CLK_END to IMX6SL_CLK_END

2013-12-31T01:36:23Z

The macro name IMX6SL_CLK_CLK_END is a little insane. Rename it to IMX6SL_CLK_END. Signed-off-by: Shawn Guo

ARM: imx: add clock support for imx6sl

2013-06-17T07:45:11Z

Add clock support for i.MX6 SoloLite. It uses the dtc marco support to define all clock IDs in imx6sl-clock.h, which will be included by both clock driver and device tree sources, so that the data will stay sync all the time between kernel and DT. Signed-off-by: Shawn Guo